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High-NA EUV is the next generation of extreme-ultraviolet lithography: it keeps the 13.5 nm wavelength used by today’s EUV scanners but raises projection numerical aperture (NA) from 0.33 to 0.55. That larger NA lets a scanner resolve smaller features in one exposure. ASML specifies 8 nm resolution for its first system, the TWINSCAN EXE:5000; the company says it can print features 1.7 times smaller and deliver 2.9 times higher transistor density than TWINSCAN NXE systems in a single exposure.
Those are scanner capability figures, not a guarantee that every layer, transistor dimension, yield, cost or finished “2 nm” chip will achieve them. High-NA EUV expands the lithography process window for selected layers, while making focus, masks, resist, overlay, metrology and defect control more demanding.
What High-NA EUV changes
Extreme-ultraviolet lithography uses 13.5 nm light to project a circuit pattern from a mask onto a resist-coated wafer. Conventional production EUV scanners use projection optics with a 0.33 numerical aperture. High-NA EUV raises that value to 0.55 while retaining the same wavelength.
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Numerical aperture describes the range of light angles that the projection optics can collect and focus. A higher value provides more information about fine pattern edges, so the aerial image can separate smaller features. ASML identifies wavelength and NA as the two primary optical resolution controls. Because High-NA changes the NA term rather than the EUV wavelength, it is an optical refinement of the existing platform, not a new light source.
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The first High-NA platform is ASML’s TWINSCAN EXE:5000. Its published specification lists 8 nm resolution. ASML’s comparison with TWINSCAN NXE systems says single-exposure features can be 1.7 times smaller and transistor density 2.9 times higher. “Single exposure” matters: the figures describe what the scanner and an appropriate process can print without splitting that layer into multiple lithography exposures.
Why a higher numerical aperture improves resolution
A useful approximation is the Rayleigh-style relationship:
critical dimension ≈ k1 × wavelength ÷ numerical aperture
k1 represents process, illumination and patterning choices. Holding wavelength and process conditions in view, increasing NA reduces the minimum printable critical dimension. Moving from 0.33 to 0.55 is a 0.55/0.33, or roughly 1.67-fold, increase in the NA term. That is consistent with ASML’s 1.7-times-smaller feature comparison, although a real production layer also depends on mask design, resist behavior, etch transfer and allowable defects.
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The equation is not a promise that a chip will contain a uniform 8 nm line. Critical dimension is a lithography metric measured under specified conditions. Designers and process engineers choose pitches, line cuts, contacts and other shapes that meet electrical and manufacturing rules. Finished transistor dimensions also depend on deposition, etch, spacer formation, source and drain construction, interconnect integration and design rules.
Conventional EUV and High-NA EUV compared
| Characteristic | Conventional EUV (NXE class) | High-NA EUV (EXE class) |
|---|---|---|
| EUV wavelength | 13.5 nm | 13.5 nm |
| Projection numerical aperture | 0.33 | 0.55 |
| Nominal single-exposure resolution | About 13 nm class; exact result is process dependent | 8 nm specified for EXE:5000 |
| Single-exposure feature comparison | Baseline for ASML’s comparison | 1.7 times smaller features than NXE, according to ASML |
| Transistor-density comparison | Baseline for ASML’s comparison | 2.9 times higher density in a single exposure, according to ASML |
| Depth of focus | Larger than 0.55-NA EUV | Imec expects it to be two to three times smaller than at 0.33 NA |
| Projection optics | Smaller and lighter than the High-NA generation | Imec describes mirrors twice as large and optics ten times heavier |
| Patterning strategy | May require multiple patterning for the tightest layers | Can reduce multi-patterning for some layers, subject to process and design limits |
| Mask, resist and metrology burden | Already demanding | Higher precision and tighter stochastic, overlay and defect requirements |
| High-volume-manufacturing status | Established EUV production platform | Systems are moving through development and early high-volume-manufacturing deployment; readiness is customer and layer specific |
| Universal throughput or cost figure | Not stated as one number across fabs | Not stated as one number across fabs |
Does High-NA EUV enable “2 nm” chips?
It can support process generations marketed with names such as 2 nm and below, but the node label is not a literal printed line width. Modern node names identify a collection of density, performance, power and design-rule targets; they do not mean every gate or metal line measures 2 nm.
High-NA’s 8 nm scanner specification therefore should not be translated into “8 nm transistors,” nor should 0.55 NA be treated as an automatic 2 nm-node switch. A chipmaker may use High-NA on only the layers where its resolution and reduced patterning justify the cost and process complexity. Other layers can continue to use 0.33-NA EUV, deep-ultraviolet lithography or multiple-patterning flows. The resulting node, density and electrical characteristics come from the complete process integration.
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High-NA can nevertheless be important for sub-2 nm development. Imec links its EXE:5200 installation to work on sub-2 nm technology through improved resolution, overlay, throughput and process stability. That statement describes a development objective, not a universal production guarantee.
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The main engineering limits
Smaller depth of focus
Depth of focus (DOF) is the vertical range over which the wafer remains acceptably in focus. Increasing NA improves lateral resolution but narrows that focus range. Imec expects 0.55-NA DOF to be two to three times smaller than at 0.33 NA.
A smaller DOF means the wafer surface, resist thickness and scanner focus must stay more tightly controlled. It increases the importance of wafer flatness, chuck and stage behavior, leveling measurements, thermal stability and focus-dose calibration. Thinner resist films can help keep the imaging stack within the focus budget, but they may provide less margin for transferring the pattern into the underlying layers. Focus errors that were tolerable on a 0.33-NA layer can become edge-placement or missing-feature defects at 0.55 NA.
Larger, heavier projection optics
High-NA projection mirrors must intercept a wider angular cone of EUV light. Imec describes the mirrors as twice as large and the optics as ten times heavier than those of the preceding generation, while still requiring extreme surface precision. Larger mass affects vibration isolation, motion control, thermal management and the mechanical design of the scanner. It also contributes to the size, complexity and capital burden of the tool.
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Anamorphic imaging and mask-field constraints
High-NA projection optics use an anamorphic imaging approach: magnification is not identical in the two wafer directions. This helps manage the larger optical angles, but it changes mask-field geometry and reticle usage compared with conventional EUV. Chip layouts, mask writing, stitching or field planning and process recipes must account for those constraints. The scanner’s nominal resolution advantage is therefore not independent of the field size and pattern orientation used by a product layer.
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Resist stochastic defects
EUV resist absorbs a limited number of photons for each printed feature. Random photon absorption, acid generation and development behavior can produce line-edge roughness, local critical-dimension variation, missing holes or bridging. Printing smaller features with a narrower focus window does not remove those stochastic effects. Resist chemistry, film thickness, dose, underlayer and post-exposure processing must be tuned with the mask and etch process rather than optimized in isolation.
Mask and defect control
A mask must preserve the intended aerial image while surviving inspection, cleaning and repeated exposures. At High-NA, mask three-dimensional effects, shadowing, pattern placement and defectivity become more consequential because the process is resolving smaller shapes. Computational patterning, source-mask optimization and correction models can improve the image, but they add modeling, data and verification work. The ecosystem challenge includes EUV masks, resist and metrology, not just the scanner.
Overlay, stage and wafer control
Overlay is the alignment of one patterned layer to the layers already on the wafer. Tighter pitches leave less positional error budget. High-NA flows therefore require highly repeatable stage motion, wafer alignment, focus and leveling, thermal control and metrology. A layer can have excellent isolated resolution yet fail integration if its placement relative to contacts, gates or neighboring metal levels is outside the overlay budget.
Throughput, cost and yield trade-offs
Reducing multi-patterning can remove masks, exposures, etch steps and alignment opportunities for selected layers. That can lower process complexity and reduce some sources of overlay accumulation. The benefit must be weighed against the price and complexity of High-NA tools, tighter process control, larger optics, new masks and resist development, and the possibility that additional inspection or rework is needed.
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There is no single universal High-NA throughput or cost number that applies to every fab, product or layer. Actual economics depend on dose, pattern density, exposure field, wafer mix, uptime, yield learning and how many 0.55-NA layers a process uses. High-NA is not automatically cheaper simply because it can print a layer in one exposure.
Where High-NA EUV stood in deployment
- 2024 development lab: ASML and imec opened a joint High-NA EUV development lab around the EXE:5000 prototype, aimed at preparing the technology for high-volume manufacturing.
- April 2024 customer installation: Intel reported installation and calibration of an EXE:5000 at its D1X facility in Hillsboro, Oregon. It said it planned to combine 0.55-NA EUV with 0.33-NA EUV for 18A and later 14A work.
- Early April 2025: ASML’s 2025 annual-report material says the first EXE:5200B shipped for high-volume-manufacturing use.
- March 18, 2026: imec announced arrival of an EXE:5200 system and connected it with sub-2 nm technology development focused on resolution, overlay, throughput and process stability.
These milestones show a transition from prototype and ecosystem qualification toward customer deployment. They do not mean that every fab, product or layer had adopted High-NA EUV, and availability and production status can change as customers qualify their own processes.
How a chipmaker decides where to use it
Process teams evaluate High-NA at the layer level, not as an all-or-nothing replacement for conventional EUV. A practical decision sequence is:
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Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →Outbyte PC Repair FREERepair Windows errors before they cause bigger problemsFix Now →- Identify the limiting layer. Determine whether a gate, contact, cut, via or metal pattern is constrained by printable pitch, stochastic defects or overlay.
- Compare patterning options. Measure the extra masks, exposures, etch steps and alignment risks of a 0.33-NA multi-patterning flow against a 0.55-NA single-exposure or reduced-patterning flow.
- Build the complete imaging stack. Co-optimize mask design, illumination, resist, underlayers, dose, focus and etch transfer; scanner resolution alone is insufficient.
- Check integration budgets. Verify DOF, wafer topography, overlay, thermal drift, defectivity, metrology capability and expected yield on actual product patterns.
- Qualify manufacturing performance. Establish stable throughput, uptime, defect control and process capability before assigning the layer to volume production.
This approach explains why a process may use both EXE and NXE scanners. High-NA provides its greatest value where the feature geometry and patterning burden justify the narrower process window; conventional tools remain suitable for layers with more relaxed requirements.
What High-NA EUV can and cannot deliver
- It can: improve optical resolution at the same 13.5 nm wavelength; print smaller features in a single exposure; potentially reduce multi-patterning on selected layers; and provide an important capability for advanced process generations.
- It cannot: guarantee a 2 nm printed line, a particular transistor density, yield, power result or cost; eliminate overlay, resist stochastic behavior, mask defects or process variation; or make every wafer layer require High-NA.
The central trade-off is straightforward: 0.55 NA expands the resolution envelope, while the smaller depth of focus and more demanding optics, masks, materials, metrology and integration narrow the manufacturing margin. High-NA EUV is consequently best understood as a system-level process platform whose value depends on how well a fab turns scanner capability into repeatable, defect-controlled production.
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