Intel Foundry has demonstrated a gallium nitride (GaN) chiplet with a silicon base just 19 μm thick, integrating GaN power transistors with silicon digital-control logic. The result is a research prototype—not an announced AI-chip product. Intel has proposed data-center power management and future wireless infrastructure as possible uses, but has not disclosed a product launch, customer deployment, or production schedule.
What is Intel’s thinnest GaN chiplet?
It is a research chiplet made from a 300 mm GaN-on-silicon wafer. The headline 19 μm measurement is the thickness of the underlying silicon substrate after thinning, not the thickness of the complete chiplet stack. Intel says the harvested chiplet retained electrically functional transistors.
Intel Foundry described the work in an announcement posted April 7, 2026, by Han Wui Then, a senior principal engineer at Intel Foundry Technology Research. The work had been presented at the 2025 IEEE International Electron Devices Meeting (IEDM). Intel Foundry’s announcement describes the chiplet and process.
How does the chiplet combine GaN and silicon?
Intel’s approach places GaN N-channel MOSHEMT power devices alongside silicon p-channel MOSFET logic devices. Layer transfer puts silicon on the GaN wafer, and shared wiring connects the power and control circuitry. In many power-electronics designs, control logic sits on a separate silicon chip. Putting control nearer to the switching devices could reduce footprint and inter-chip routing, but Intel has not reported measured whole-system savings from this prototype.
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How Intel thinned the silicon base
Intel says it used stealth dicing before grinding (SDBG): a controlled laser forms microscopic fracture lines inside the wafer, then mechanical grinding reduces its thickness. The reported 19 μm refers to the resulting silicon base. Intel also illustrates a prototype chiplet flipped and attached to a base wafer; the image demonstrates an assembly concept, not a commercially deployed package.
What performance did Intel report?
The announcement reports device- and circuit-level measurements. They are not benchmarks of an AI accelerator, a complete power-delivery system, or a production chip.
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| Measure | Intel’s reported result | What it describes |
|---|---|---|
| Silicon-base thickness | 19 μm | Underlying silicon substrate of the harvested chiplet, not total stack thickness. |
| Wafer diameter | 300 mm | GaN-on-silicon wafer used for the work. |
| Minimum gate length | 30 nm | Reported transistor dimension. |
| Voltage blocking | Up to 78 V | Reported transistor capability. |
| Cutoff frequency | More than 300 GHz | Transistor RF measurement, not AI computing speed. |
| Inverter switching | 33 ps | Intel says inverter speed results were consistent across the 300 mm wafer; this is a circuit measurement, not an application benchmark. |
These figures are Intel’s reported results in its April 2026 announcement. The source does not give a comparable rival chiplet result or a system-level benchmark.
How could a GaN chiplet help AI chips?
AI systems need power conversion close to high-demand processors. GaN is attractive for power conversion because it can switch quickly and handle high voltage, while silicon logic can perform digital control. Combining the two on a chiplet could allow control to sit nearer to power switching and potentially avoid a separate companion chiplet. Those are design motivations, not demonstrated savings or confirmed use in a shipping AI processor.
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Intel also identifies high-frequency RF as a potential application area. Its announcement presents data-center point-of-load power and future wireless infrastructure as possibilities; it does not confirm deployments in AI accelerators or 5G/6G base stations.
What does Intel’s reliability evidence establish?
Intel says it studied time-dependent dielectric breakdown (TDDB), positive bias temperature instability (pBTI), high-temperature reverse bias (HTRB), and hot-carrier injection (HCI), describing the results as promising against required metrics. The public announcement does not publish lifetime values or detailed qualification data. Reliability testing is therefore evidence of research evaluation, not proof of customer qualification or commercial readiness.
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What did Intel report after the 19 μm demonstration?
In June 2026, Intel described later GaN-and-silicon power-management research on a 300 mm platform with UC San Diego collaborators. The sources characterize the digital-control result differently: Intel Foundry’s VLSI 2026 summary reports multi-thousand-gate circuits, while an Intel Newsroom summary dated June 16, 2026 describes an approximately 1,000-gate control block. Neither account establishes mass production of the specific 19 μm chiplet.
Is Intel’s GaN chiplet available yet?
The cited Intel announcements do not provide a price, ordering path, customer-sampling status, or production timeline. They describe research work and possible applications, not a purchasable chiplet or confirmed customer product. Whether Intel will commercialize this process, which customers could access it, and whether the exact 19 μm design will be sampled remain undisclosed in those sources.
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