DNNDK v3.0 documented Avnet Ultra96 as an evaluation board for running neural-network inference on a Xilinx DPU. The workflow split into two parts: prepare and compile a model for the board’s specific DPU configuration, then deploy and run an application on Ultra96. This is a historical 2019 toolchain guide—not confirmation that a particular Ultra96 revision, image, host setup, or software package remains compatible today.
What the Ultra96 and DNNDK setup did
DNNDK was a software stack for inference using a Deep-learning Processing Unit (DPU), a configurable accelerator implemented in programmable logic. Xilinx’s DNNDK User Guide UG1327 v1.4, dated April 29, 2019, explicitly listed Avnet Ultra96 as a supported evaluation board alongside ZCU102 and ZCU104. That statement describes the v3.0-era package documentation; it is not a present-day support guarantee.
The later DPU IP Product Guide PG338 v3.0, dated August 13, 2019, describes DNNDK as “a full-stack deep learning toolchain for inference with the DPU.” Its components included DECENT for model compression and quantization, DNNC for compilation, N2Cube for runtime, and DPU Profiler. The guide says DNNC produced an offline instruction file with an .elf suffix. That file was tied to the DPU architecture, the target network, and AXI data width, so compilation depended on the actual DPU configuration.
How the historical workflow was organized
Model preparation and compilation happened separately from application execution on the board. The Ultra96 workshop repository describes examples using ResNet-50 classification, Densebox face detection, and SSD object detection. Its general sequence was to quantize a model, compile it with dnnc to produce DPU kernel output, transfer that output to Ultra96, then compile and run application code on the board. The workshop is instructional historical material, not a vendor compatibility matrix, and its exercises may depend on prepared images and artifacts.
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- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
- Check the target configuration. Identify the exact Ultra96 revision, board image, and DPU configuration you intend to use. The compiler’s output is not independent of DPU architecture or AXI data width.
- Prepare the model. The workshop examples include quantization before compilation. DECENT was the DNNDK component associated with compression and quantization.
- Compile for the DPU. DNNC (invoked as
dnncin workshop instructions) generated DPU kernel output, including the architecture-dependent offline instruction file. - Build and run the application on Ultra96. Transfer the generated output and use the board-side runtime and libraries appropriate to that board. The DNNDK guide notes that board utilities, DPU drivers, runtime, and development libraries differed by board.
A workshop example handled a layer unsupported by the DPU with CPU execution. That illustrates a possible division of work in that example; it does not establish that every model or unsupported layer will run automatically on the CPU.
Host and board requirements in the DNNDK v3.0-era documentation
The DNNDK v3.0 package guide specified host tools for 64-bit Ubuntu 14.04 LTS or 16.04 LTS and identified separate board folders for device-specific utilities and DPU components. These are historical compatibility details, not recommended operating systems for a new deployment. The guide identifies a package named xilinx_dnndk_v3.0_yymm.tar.gz.
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- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
Version labels also need care: PG338 is the DPU IP guide for version 3.0, while UG1327 v1.4 is the DNNDK user guide documenting the v3.0 package. PG338 said DNNDK v3.1 was the latest package when that guide was written. Those labels do not mean that all components from different releases can be freely combined.
What the examples do—and do not—establish
The workshop repository’s SSD example specifies a 480×360 input and claims 28 frames per second. Treat that as the repository’s claim for its described demo, not an independently verified benchmark or a general Ultra96 performance figure. Performance depends on the model, input, DPU configuration, and software setup; the cited material does not provide a cross-model performance comparison.
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The Ultra96 development board is the central hardware item in this workflow. A camera appears in a system example and is used in a face-detection exercise, so it is relevant only when following a camera-based demo. An SD card appears in a separate DPU product-guide example-design requirement; neither source establishes that a camera or SD card is mandatory for every inference project.
DNNDK versus later PYNQ and Vitis AI paths
Later tools are distinct deployment routes, not drop-in replacements for DNNDK artifacts. The Xilinx DPU-PYNQ repository names Ultra96v1 and Ultra96v2 entries and says its release supports PYNQ 3.0 and Vitis AI 2.5.0. That describes the PYNQ project’s version combination; it does not establish DNNDK support for those board revisions or prove that a DNNDK .elf can be used in that flow. AMD’s Vitis AI repository describes a broader inference stack, but the cited information does not provide a complete DNNDK migration table.
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- Altera 10CL016 FPGA with 16,000 Logic Elements. This FPGA Development Kit requires an external JTAG Programmer. The Cyclone 10 FPGA is a powerful mid-range chip from Altera. It contains 504 Kbits of SRAM Memory. This chip is perfect for implementing soft core processors such as a RISC-V.
- The CycloFlex includes Three Seven Segment Displays which are directly drivable from FPGA I/O pins. 65 Inputs/Outputs from the FPGA available at board connectors. There are seven Green User LEDs that can be controlled directly from FPGA pins. One RGB LED is also included. Two Pushbuttons are available for input to user code.
- One 50MHz oscillator provides all precision clocking needs on the CycloFlex Board. The FPGA includes four DLL's that provide both frequency multiplier and divider. This provides a broad range for clocking options for user code.
- There are two power options for the CycloFlex: USB-C connector or Barrel Connector. The USB-C options allows +5VDC through the USB 2.0 specification. Any USB-C charger or Laptop will properly power the CycloFlex. The Barrel Connector accepts +4.5 to +5.5VDC at 3Amps.
- The CycloFlex Development Kit comes complete with downloadable User Manual, Data Sheet, Drivers, Schematics, and compiled, source code, projects. The downloadable DVD has an entire tutorial on Getting Started with FPGA. It walks the user through getting the ModelSim/Questa simulation tool setup. It has guides to creating simple code for FPGAs through more advanced Test Benches. It also includes full projects with source code to communicate with the CycloFlex from a Windows PC.
| Question to check | DNNDK v3.0-era path | Later DPU-PYNQ path |
|---|---|---|
| Platform evidence | UG1327 v1.4 (April 29, 2019) lists Avnet Ultra96; it does not establish support for every revision or current availability. | The repository names Ultra96v1 and Ultra96v2 entries; this is evidence for that project path, not DNNDK compatibility. |
| Software versions | Host tools documented for 64-bit Ubuntu 14.04 or 16.04; board components vary by board. | README states support for PYNQ 3.0 and Vitis AI 2.5.0 in its release context. |
| Compiler output and deployment | DNNC generates DPU-specific offline instructions and kernel output; board runtime and DPU configuration matter. | Not established by the cited README as interchangeable with DNNDK output; follow the project’s own artifacts and instructions. |
| Evidence type | Vendor documentation for a 2019 release, plus a historical workshop with example instructions. | A separate repository route; its listed support does not certify the older DNNDK stack. |
What to verify before attempting a build
The 2019 guides establish what the documented releases targeted at the time, but do not settle whether the complete toolchain can now be obtained and run together. Before investing in a setup, verify the exact board revision, available board image, DNNDK package, DPU IP configuration, and host environment as one compatible combination. Also ensure the compiler targets the DPU architecture actually present in the image; changing the architecture, network, or AXI data width requires regenerating the offline instructions.
Quick Recap
Best Value
- Altera Cyclone IV FPGA includes 6,000 Logic Elements with two clock multipliers. The Cyclone IV FPGA is the perfect balance of inexpensive cost versus plentiful logic cells, 20KBytes of SRAM, and General Purpose Input/Output pins. This is a great board to learn how to program FPGA's.
- Built in programmer cable allows configuring the FPGA with a single USB-C cable. The DPL can be powered from the USB cable or from the Barrel Connector. A separate JTAG header can also be used to program the FPGA using a compatible USB Blaster cable.
- 6x6 LED Array allows character and animations to be displayed at ultra fast speed. LED blocks can be individually turned on/off to allow LED signals to be used as I/O's
- 70 Inputs/Outputs originating at the FPGA are available at Stackable Headers organized around the edge of the board. The user can configure these I/O's using the FPGA project code.
- The DPL contains two oscillators, 66MHz and 100MHz. The 66MHz oscillator is used to provide clocking for the EPT ActiveHost USB communications core. The 100MHz oscillator can be used by the user clocked up using one of the onboard Clock-DLL modules.
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