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Deep ultraviolet (DUV) lithography is a way to project tiny circuit patterns onto silicon wafers using ultraviolet light. A scanner shines light through a patterned reticle, reduces and focuses the image onto a light-sensitive coating, and exposes one area of the wafer at a time. Chemical processing then develops the coating, and later steps transfer the pattern into the material beneath it. Lithography is one repeated step in chipmaking—not a process that creates a finished transistor by itself.

How DUV lithography patterns a wafer

The reticle, often called a mask, carries a blueprint of a circuit layer. In ASML’s description, the reticle pattern is four times larger than the pattern intended for the chip. Projection optics reduce that image by 4:1 and focus it onto photoresist, a temporary light-sensitive coating on the wafer.

A modern step-and-scan system exposes the wafer in strips. It illuminates a narrow portion of the reticle while the reticle and wafer move in opposite directions, keeping the projected image aligned as it scans. After the scanner completes a die area, the wafer steps to the next position and the exposure is repeated. A NIST-hosted lithography handbook chapter describes this scan-and-step approach and the chemical processing used afterward to turn the latent resist image into a physical pattern.

Exposure changes the resist chemically; it does not carve the silicon directly. Baking and developing reveal the resist pattern. Etching can then remove exposed underlying material, while other steps—such as ion implantation—can modify selected regions. The remaining resist is eventually removed.

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Where lithography fits in chipmaking

A chip is built through repeated cycles of material deposition, resist coating, lithography, baking and developing, etching or other processing, and resist removal. The pattern from one lithography step determines where a later operation acts. ASML’s 2024 annual report says lithography may be repeated 100 times or more across a complete chip, depending on the design and process.

Different layers of the same chip may use different lithography methods. DUV remains a workhorse: ASML says DUV systems produce the majority of microchip layers, including layers on chips that also use EUV. It is therefore misleading to picture an advanced chip as being made entirely with EUV.

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DUV wavelengths and what they mean for feature size

DUV scanners use excimer lasers. Two important sources are krypton-fluoride (KrF) at 248 nanometers and argon-fluoride (ArF) at 193 nanometers. ASML’s wavelength explainer gives examples of modern KrF systems producing features down to 80 nm and 193 nm ArF enabling 38 nm features. Those are explanatory examples, not universal limits for every process or scanner.

Shorter wavelength can help print smaller features, but wavelength alone does not determine resolution. The Rayleigh relationship also depends on numerical aperture (NA)—how effectively the optics collect and focus light—and process factors such as resist behavior. A chip’s marketed “node” is not a direct statement of the minimum feature a particular lithography tool can print.

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Why some DUV scanners use water

Immersion DUV places a thin layer of water between the final projection lens and the wafer. Because water has a higher refractive index than air, the optical system can achieve a higher NA and improve resolution without changing the light’s wavelength. The light remains 193 nm or 248 nm; water is not a wavelength converter.

ASML reports an NA of 1.35 for its highest-resolution DUV machines. Its 2024 annual report, published in 2025, lists the TWINSCAN NXT:2150i as a 193 nm ArF system with NA 1.35 and a throughput of up to 310 wafers per hour. That is a vendor-reported specification for that named model, not a rate that applies to every DUV tool.

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How multi-patterning extends DUV

A dense layout may be too intricate to print in one exposure. Multi-patterning divides it into simpler interlaced patterns, which are exposed in separate steps and combined in the finished layer. This lets DUV handle patterns smaller or denser than a single exposure could resolve, but it adds process steps and makes overlay—the precise alignment of one exposure with another—critical. Misalignment can compromise the intended pattern.

ASML says EUV can simplify manufacturing compared with complex multi-patterning strategies using DUV immersion. That is a trade-off rather than a simple replacement: a chipmaker chooses lithography by layer, pattern complexity, process integration, and manufacturing requirements. DUV remains useful for many layers even when EUV is selected for especially intricate ones.

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DUV and EUV compared

Approach Light source and optical path Resolution context Patterning trade-off
DUV, including dry systems Common advanced sources are 248 nm KrF and 193 nm ArF; dry systems do not use the water immersion layer. Depends on wavelength, NA, and process conditions. ASML gives 80 nm as a modern KrF feature example and 38 nm as an example enabled by 193 nm ArF; neither is a universal tool limit. Some dense patterns require multiple exposures, increasing steps and overlay demands.
Immersion DUV Typically 193 nm ArF in the cited high-resolution example, with water between the final lens and wafer. Water enables higher NA; ASML reports NA 1.35 for its highest-resolution DUV machines. Can extend DUV resolution, but difficult layouts may still require multi-patterning.
EUV 13.5 nm light; ASML says this wavelength is more than 14 times shorter than DUV light. Shorter wavelength can support smaller features, though system and process factors still matter. Can reduce reliance on complex DUV immersion multi-patterning for some patterns; DUV and EUV may both be used on one chip.

What DUV’s limits do—and do not—tell you

There is no single universal “DUV resolution limit” established by these examples. The printed result depends on the specific optical system, numerical aperture, resist and process conditions, and whether the design is split across exposures. Nor does a named chip node by itself identify the feature size printed by one exposure.

The NIST-hosted handbook chapter describes a typical leading-edge scanner example as requiring more than 50 full-chip exposures on a 300 mm wafer and processing about 100 wafers per hour. This is contextual technical description, not a current benchmark for a particular scanner. For comparison, the up-to-310-wafers-per-hour figure above is specifically ASML’s reported maximum for the NXT:2150i.

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