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Apple’s A9X was not simply a faster A9. It was a tablet-focused redesign for the first iPad Pro: a reported 147 mm² TSMC 16 nm FinFET die with 12 PowerVR Series 7-family GPU units, two CPU cores and no L3 cache. Most of the extra silicon went to graphics and the memory system, matching the iPad Pro’s much larger, higher-resolution display rather than adding more CPU cores.

Apple introduced the 64-bit A9X with the 12.9-inch iPad Pro in September 2015 and later used it in the 9.7-inch model. Apple’s public material describes “desktop-class” CPU performance and “console-class” graphics, but those are product-positioning claims, not standardized benchmark results. The internal specifications below come from Chipworks die analysis reported at the time, Apple’s technical documentation, and a teardown; they should not be confused with a complete Apple-published block diagram.

What the A9X was

The A9X was an Apple-designed 64-bit ARM-based system-on-chip (SoC) built for the first-generation iPad Pro. Apple announced the 12.9-inch tablet on September 9, 2015, with sales beginning in November. Its product brief emphasized a large canvas for productivity, illustration, engineering, medicine, education, gaming and video, along with Apple Pencil support and a four-speaker system. The 12.9-inch display runs at 2732×2048, or about 5.6 million pixels.

Apple later fitted the A9X to the 9.7-inch iPad Pro. Apple’s specification page identifies that model as using an “A9X chip with 64-bit architecture” and an embedded M9 coprocessor. It lists a 2048×1536 display at 264 ppi and storage capacities of 32 GB, 128 GB and 256 GB. Apple rated battery life at up to 10 hours under its stated usage conditions. See Apple’s 2015 announcement and the 9.7-inch technical specifications.

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The A9X sits between the phone-oriented A9 and the later A10X in Apple’s tablet line. The “X” suffix did not mean a fixed recipe such as “the phone chip plus two CPU cores”; the A9X shows Apple changing the balance of CPU, GPU, cache and memory for a different product.

What the die analysis found

Chipworks’ examination, reported in contemporary coverage, identified an approximately 147 mm² A9X die manufactured by TSMC on a 16 nm FinFET process. That is a measured or estimated result from an analyzed sample, not an Apple-published specification. The historical AnandTech article associated with the report was titled “More on Apple’s A9X SoC: 147mm2@TSMC, 12 GPU Cores, No L3 Cache,” published November 30, 2015; its old URL now redirects to the AnandTech forums. A contemporary summary of the findings is available from GIGAZINE, while the historical reference is AnandTech’s original URL.

A die this large carried real manufacturing trade-offs: larger dies generally cost more per usable chip because a defect is more likely to land somewhere on the die and because fewer dies fit on a wafer. Apple nevertheless had reasons to accept that expense. A tablet offered more battery and thermal volume than an iPhone, and the iPad Pro’s display imposed a much larger graphics and memory workload.

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Twelve GPU units explain most of the size

The most important finding was the graphics block. The Chipworks analysis identified 12 GPU units or clusters associated with the PowerVR Series 7 family—roughly twice the A9’s reported GPU configuration. Secondary sources use “GPU cores,” “clusters” and “PowerVR cores” somewhat interchangeably; these terms describe parallel graphics blocks, not 12 general-purpose CPU cores. The implementation also did not map neatly to a standard, off-the-shelf Imagination roadmap part, so it is safer to describe it as Apple’s customized implementation of a PowerVR-based architecture rather than call the GPU wholly Apple-designed.

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The reason for spending so much area on graphics is visible in the product context. Driving 2732×2048 pixels requires substantially more rendering and data movement than driving the iPhone 6s display. High-resolution composition, 3D games, drawing, video effects and professional creative applications all benefit from parallel GPU throughput. The A9X therefore invested die area where the iPad Pro would use it most: graphics engines and the paths feeding them.

Why two CPU cores instead of three?

Die analysis reported two CPU cores in the A9X, while the preceding A8X used three. That is not a contradiction in a high-performance design. Core count is only one variable; a smaller number of larger or faster cores can perform well in lightly threaded work, while power and area saved from an additional core can be redirected to graphics, cache, memory interfaces or sustained operating points.

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Apple did not publicly explain the decision. The defensible conclusion is that the A9X targeted a different balance from the A8X: strong single-threaded and everyday responsiveness, plus a much larger graphics and memory budget. It should not be described as a 12-core processor; the “12” finding refers to GPU units.

No L3 cache: a cache-and-bandwidth trade-off

The same analysis reported that the A9X lacked the L3 cache present in the A9 design. Apple did not announce a reason. The most plausible interpretation is a deliberate trade-off: omitting a shared L3 saved on-die area and some power, while a wider or higher-bandwidth memory system supplied data to the enlarged GPU and CPU complex.

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Cache and bandwidth solve different problems. A cache keeps recently used data close to the cores and can reduce average latency; bandwidth determines how quickly the SoC can stream data between the chip and external memory. GPU-heavy workloads often need sustained streaming bandwidth, so a design can choose to spend silicon on memory interfaces and graphics resources rather than on another cache level. This explanation is an architectural inference from the reported layout, not a statement Apple made publicly, and the absence of L3 does not automatically imply lower performance.

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Memory: capacity is not bandwidth

The A9X’s graphics expansion makes its memory subsystem especially important. More GPU units can only stay busy if the system can feed them textures, frame buffers and intermediate results. That is why discussions of the missing L3 cache should be paired with memory bandwidth rather than treated as an isolated specification.

  • RAM capacity is how much data and code the device can hold at once.
  • Memory bandwidth is the rate at which the SoC can move data to and from memory.
  • GPU count is the amount of parallel graphics hardware available to process that data.

A teardown of one 9.7-inch iPad Pro identified the Apple APL1021 A9X and 2 GB of LPDDR4 memory. That finding applies to the model examined by iFixit, not automatically to every A9X-equipped iPad Pro or to the 12.9-inch version. The teardown PDF is available at iFixit. Apple’s public specification page does not state RAM capacity for the 9.7-inch model.

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A9X versus A9

Area A9 (iPhone 6s generation) A9X (first iPad Pro generation)
Product target Phone-class performance and efficiency Large-screen tablet and creative workloads
CPU Two Apple-designed CPU cores, according to contemporary analysis Two CPU cores, according to Chipworks die analysis
GPU Smaller configuration 12 GPU units/clusters reported by die analysis
L3 cache Present in the reported A9 design Reported absent
Die size Smaller than the A9X; an exact value is not established in the supplied evidence Approximately 147 mm², measured or estimated from the analyzed die
Process Production involved more than one foundry in contemporary reporting Analyzed sample reported as TSMC 16 nm FinFET
Design emphasis Balanced phone CPU, GPU and power budget Expanded graphics and memory-throughput budget

Apple’s claim that the A9X delivered desktop-class CPU performance and console-class graphics describes its intended class of experience. It is not evidence that every application ran at a single multiplier, and it should not be rewritten as “twice as fast” in all tasks.

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A9X versus A8X: the X strategy changed

The A8X used three CPU cores, whereas the A9X reportedly used two. At the same time, the A9X roughly doubled the GPU-unit count relative to the A9 and moved to a newer process with a more capable memory system. This contrast shows that Apple’s tablet strategy was not simply to add CPU cores to the iPhone design. For the first iPad Pro, graphics throughput, display composition and memory traffic were more valuable uses of silicon than a third CPU core.

What is official, what is reconstructed

Information Status
A9X name, 64-bit architecture, M9, product models and display specifications Apple-published specifications
“Desktop-class CPU” and “console-class graphics” positioning Apple marketing language, not a standardized benchmark
Approximately 147 mm² die, TSMC 16 nm, 12 GPU units, two CPU cores and no L3 Reverse-engineered findings from an analyzed sample, reported by Chipworks/AnandTech coverage
2 GB LPDDR4 in a 9.7-inch unit iFixit teardown observation for that specific model
Why L3 was omitted Reasoned architectural interpretation; Apple did not publish an explanation

Why the A9X mattered

The A9X established an important pattern for Apple’s tablet silicon. Rather than treating an iPad as an iPhone with a larger screen, Apple built a SoC around the tablet’s workload: millions more display pixels, sustained graphics, stylus input, multitasking and creative software. The result was a comparatively large mobile die whose defining choices were a very large GPU, high memory throughput and a leaner CPU configuration.

Those choices also explain why specifications must be handled carefully today. The 12.9-inch and 9.7-inch iPad Pro models did not necessarily share identical memory configurations, clocks or performance behavior. Die-analysis terminology is not always equivalent across sources, and the 16 nm description applies to the reported sample rather than proving that every production die had identical characteristics. The A9X’s historical significance lies less in one headline number than in the design balance it reveals: Apple was willing to spend substantial silicon area on graphics to make the first iPad Pro a tablet-class computer.

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