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X-FAB’s reported ISOMOS1 module adds a 25 V isolation class to its 180 nm XH018 process. It is designed to shrink transistor-isolation structures in SPAD pixels, potentially leaving more room for optical area or tighter layouts. In one specific array example, Embedded reports about 25% less total area and a 30% higher fill factor than with older isolation options; those figures are not guarantees for other layouts.

What is X-FAB’s ISOMOS1 isolation class?

ISOMOS1 is an isolation class reported as an addition to X-FAB’s XH018, a 180 nm process that supports single-photon avalanche diode (SPAD) integration. The announcement describes it as a 25 V class intended to reduce the size of transistor isolation structures. Embedded’s report says the module integrates with X-FAB’s existing SPAD technology offerings without adding a mask layer. Embedded’s report does not provide the underlying technical note or detailed design rules, so treat these as announcement claims rather than independently verified process specifications.

Why transistor isolation geometry matters in SPAD arrays

A SPAD pixel combines a light-sensitive diode with surrounding circuitry. Isolation structures keep transistors electrically separated, but they also take up layout area. If those structures can be made smaller, a designer may be able to fit pixels more closely or devote a greater share of a pixel to its optical detection area. The useful outcome depends on the full pixel layout and design rules: a smaller isolation structure alone does not establish a particular array pitch, detection efficiency, or system-level performance.

What area and fill-factor improvement does the example report?

For a 4 × 3 SPAD array with 10 × 10 µm² optical areas, Embedded reports approximately 25% less total area and a 30% improvement in fill factor with ISOMOS1 compared with older isolation options. Both figures apply to that described example. The report does not provide a complete test method or independent validation, and it does not establish that other pixel geometries will see the same changes.

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For a process evaluation, designers should compare like-for-like layouts and confirm the relevant definitions and constraints in the current process design kit (PDK). Useful comparison points include total pixel area, optical fill factor, array pitch, isolation-voltage class, mask count, SPAD active area, wavelength response, and applicable design rules. The report supplies only the example area and fill-factor comparison, the 25 V class, and the no-additional-mask claim; it does not provide a full data set for ranking process options or foundries.

Which X-FAB process supports SPAD integration?

The reported platform is XH018, X-FAB’s 180 nm process. Embedded says its SPAD offering includes devices with active detection areas from 10 µm to 20 µm and a diode optimized for near-infrared light. These are platform details reported in the announcement, not evidence that ISOMOS1 has been validated for every device or wavelength application.

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What should designers verify before using ISOMOS1?

Embedded says PDKs and models incorporating ISOMOS1 are available to designers, but its report does not state a PDK revision, design-rule details, qualification status, or access terms. Before making layout or tape-out decisions, confirm those particulars and the 25 V class’s applicable constraints with current X-FAB documentation or the foundry. The report does not establish pricing, commercial terms, measured photon-detection probability, or performance in a named end product.

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Where SPAD technology is used

SPADs are used or considered for applications including direct time-of-flight sensing, LiDAR, 3D imaging, AR/VR depth sensing, quantum communication, biomedical sensing, industrial distance measurement, and robotics. This is context for SPAD technology generally; the announcement does not demonstrate ISOMOS1 performance in each of these applications.

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