Recommended Free Tools
RowHammer is becoming harder to defend against because newer DRAM can be disturbed by repeated row activations, while familiar safeguards such as Target Row Refresh (TRR) and on-die error correction do not reliably catch every attack pattern. DDR5 improves memory defenses, but tests of 15 SK Hynix DDR5 DIMMs show that those defenses are not a guarantee. The results do not establish that every DDR5 module is vulnerable—or that modules from other vendors are safe.
What RowHammer does
DRAM stores data as electrical charge in memory cells. That charge naturally leaks and must be refreshed. RowHammer exploits interference between neighboring rows: repeatedly activating an aggressor row can make charge drain prematurely from a victim row, flipping a bit without directly writing to that victim.
A bit flip is a reliability problem; it becomes a security problem when software can trigger it and use the resulting memory corruption to gain privileges or expose protected data. Google’s Security Blog describes the underlying disturbance and concludes that current mitigations are not sufficient.
Why the challenge is growing
As memory cells become smaller and more tightly packed, the physical margin against disturbance shrinks. The number of activations needed to provoke a bit flip—the RowHammer threshold—can fall, while the number of rows potentially affected, or blast diameter, can grow. A defense that watches only a few likely targets may therefore miss activity that reaches other rows.
#1 Best Overall
- Disclaimer: Maximum Speed requires overclocking/PC BIOS adjustments. Maximum speed and performance depend on system components, including motherboard and CPU
- Hand-sorted memory chips ensure high performance with generous overclocking headroom
- VENGEANCE LPX is optimized for wide compatibility with the latest Intel and AMD DDR4 motherboards
- A low-profile height of just 34mm ensures that VENGEANCE LPX even fits in most small-form-factor builds
- A solid aluminum heatspreader efficiently dissipates heat from each module so that they consistently run at high clock speeds
ETH Zurich’s REGA project characterizes both trends as worsening and describes RowHammer as an unsolved security problem inside DRAM. The combination matters: lower thresholds can make attacks easier to trigger, and a larger blast diameter makes it harder for a mitigation to know in advance which rows need protection.
Why DDR5’s safeguards do not settle the issue
TRR can miss attack patterns
Target Row Refresh attempts to detect activity against selected aggressor rows and refresh nearby rows before disturbance causes corruption. But TRR implementations are proprietary and may track only selected rows or patterns. ETH Zurich’s Phoenix work reverse-engineered TRR behavior and used refresh-sampling blind spots, together with self-correcting synchronization for long attack patterns, to evade those mitigations.
On-die ECC is not a security guarantee
On-die error-correcting code (ODECC) can correct some errors within a DRAM chip, but it does not make the memory immune to RowHammer. ETH Zurich explains that ODECC corrects bits after data is written or after a delay; with prolonged hammering, errors can accumulate. Error correction is a useful reliability layer, not proof that an attacker cannot cause exploitable corruption.
Rank #2
- Disclaimer: Maximum Speed requires overclocking/PC BIOS adjustments. Maximum speed and performance depend on system components, including motherboard and CPU
- AMD EXPO & Intel XMP 3.0 Compatible Only: Dual memory profiles allow you to easily select optimized settings for your platform, whether you’re running an AMD or Intel processor
- Dynamic RGB Lighting: Individually addressable RGB lighting delivers vibrant effects through a sleek, understated panoramic diffuser
- Onboard Voltage Regulation: Onboard voltage regulation for reliable power at high frequencies
- Maximum Bandwidth and Tight Response Times: Optimized for peak performance on the latest AMD and Intel DDR5 motherboards
Mitigation depends on more than the DIMM
Protection also depends on the memory controller, CPU, firmware and operating system. In the separate McSee study, the authors reported that neither Intel nor AMD CPUs sent DDR5 Refresh Management (RFM) commands in the systems they tested, although one-third of the DDR5 devices they tested required RFM for proper RowHammer mitigation. That result describes those tested systems and devices; it should not be read as a finding about every current platform.
Quick wins for a faster PC:
Repair Windows errors before they cause bigger problemsFix Now →Scan for outdated or missing drivers - takes under a minuteDriver Scan →What the Phoenix results show—and what they do not
ETH Zurich tested 15 SK Hynix DDR5 DIMMs manufactured between December 2021 and December 2024. All 15 were vulnerable to one of two Phoenix attack patterns. For the shorter pattern, the researchers reported an average of 4,989 bit flips. These results demonstrate that DDR5 and its tested mitigations did not stop the attacks on those modules and platforms; ETH Zurich cautions that the findings do not establish whether other vendors’ devices are vulnerable or protected.
The researchers also demonstrated security consequences beyond isolated bit flips. All tested DIMMs were vulnerable to a page-table-entry attack; 73% were vulnerable to an RSA-2048 key attack against a co-located virtual machine; and 33% were vulnerable to an attack on the sudo binary. In separate exploit demonstrations, ETH Zurich reported privilege escalation in 109 seconds on a PC with default settings and an average of 5 minutes 19 seconds to reproduce the Rubicon privilege-escalation exploit. Those timings belong to the researchers’ demonstrations, not to a promise that an attack will take the same time on another computer.
Rank #3
- Boosts System Performance: 32GB DDR5 RAM laptop memory kit (2x16GB) that operates at 5600MHz, 5200MHz, or 4800MHz to improve multitasking and system responsiveness for smoother performance
- Accelerated gaming performance: Every millisecond gained in fast-paced gameplay counts—power through heavy workloads and benefit from versatile downclocking and higher frame rates
- Optimized DDR5 compatibility: Best for 12th Gen Intel Core and AMD Ryzen 7000 Series processors — Intel XMP 3.0 and AMD EXPO also supported on the same RAM module
- Trusted Micron Quality: Backed by 42 years of memory expertise, this DDR5 RAM is rigorously tested at both component and module levels, ensuring top performance and reliability
- ECC Type = Non-ECC, Form Factor = SODIMM, Pin Count = 262-Pin, PC Speed = PC5-44800, Voltage = 1.1V, Rank And Configuration = 1Rx8
What protection options mean in practice
| Approach | How it works | What the evidence supports |
|---|---|---|
| TRR | Tracks selected aggressor activity and refreshes nearby rows. | Useful defense, but Phoenix evaded the tested TRR behavior through blind spots in refresh sampling. It is not a guarantee against every pattern. |
| On-die ECC (ODECC) | Corrects some errors within the DRAM chip. | Can help with errors, but ETH Zurich says delayed correction can allow errors to accumulate under prolonged hammering. |
| Higher refresh rate | Refreshes memory more frequently, reducing the time for disturbance effects to build. | Tripling refresh stopped bit flips on Phoenix’s test systems, at a measured performance cost described below. It is not proof of safety on all DDR5 systems. |
| PRAC | Per-Row Activation Counting tracks every row activation and alerts the system when a count is excessive. | Google describes PRAC as an approved JEDEC standard planned for upcoming DDR5 and LPDDR6 versions; it is not generally a fix that can be added to already-deployed DRAM. |
Higher refresh: a tested operational mitigation
On the systems ETH Zurich tested, tripling the refresh rate—approximately tREFI = 1.3 microseconds—stopped bit flips from the Phoenix patterns. The change caused an 8.4% SPEC CPU2017 performance overhead in the researchers’ measurement. That is a specific test result, not a universal performance estimate or a guarantee that the same setting protects a different memory subsystem.
PRAC: the standards direction
PRAC is designed to count activations for every row rather than infer risk from a sampled set of patterns. Google describes it as an approved JEDEC standard planned for upcoming DDR5 and LPDDR6 versions. Because deployed DRAM generally cannot be updated to add this capability, the transition depends on future memory and system designs; vulnerable modules may remain in service for years.
Research proposals are not shipping guarantees
ETH Zurich’s REGA/REGAm proposal is designed to protect independently of blast diameter. The project reports 2.1% area overhead and modeled performance overhead ranging from 0% to 3.7%, depending on threshold and configuration. Those are research results, not measured guarantees for products currently in use.
Quick Recap
What PC and server owners can do
For an individual PC owner
- Do not assume that a DDR5 label, TRR, or on-die ECC means RowHammer is impossible. Conversely, the Phoenix results do not prove that your particular DIMM is vulnerable.
- Install relevant BIOS/UEFI and platform firmware updates offered by your computer or motherboard vendor. Ask the vendor whether the update changes RowHammer mitigation behavior for your specific system; do not infer protection from the presence of an update alone.
- Avoid changing memory refresh timings or related firmware settings unless the system vendor documents the change for your platform. A setting that helped in a research test is not automatically safe, compatible, or effective on another system.
For server and cloud operators
- Assess the complete memory subsystem, not just the DRAM generation: include DIMMs, CPU and memory controller, firmware configuration, and the operating system or hypervisor.
- Ask platform and memory suppliers which RowHammer mitigations are implemented, whether RFM is used where required, and whether their claims cover the installed hardware and firmware versions.
- If considering higher refresh as an operational response, validate it on the actual platform and workload. The Phoenix result establishes a performance trade-off on the researchers’ test systems, not a universal setting or protection guarantee.
- Revisit the assessment when replacing memory or updating platform firmware. Mitigation quality is shared across DRAM vendors, CPU and firmware vendors, software developers, and system operators.
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
