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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteThe memory wall is the gap between how quickly a processor can calculate and how quickly memory and interconnects can deliver the data it needs. When data arrives too slowly, compute units wait instead of doing useful work. In AI, that gap can occur within a chip, between a processor and its memory, or between accelerators working together.
What the memory wall means for AI
A conventional processor and its memory are separate parts of a system. The processor fetches data, operates on it, and may write results back. Those transfers take time and consume bandwidth and energy. AI accelerators can perform many operations quickly, but model weights, activations, and other working data still have to reach their compute units.
The memory wall is not simply a shortage of memory capacity or arithmetic power. It is a data-supply and data-movement problem. Capacity determines how much information can be stored; bandwidth determines how quickly it can be supplied; locality determines how far it must travel; and interconnects determine how efficiently separate components can communicate.
That is why adding more compute does not automatically make an AI workload faster. If the compute units cannot get data in time, some of their potential performance goes unused. The bottleneck may be inside a chip’s memory hierarchy, between the chip and external memory, or in communication between accelerators.
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Why compute has pulled ahead of memory bandwidth
In their 2024 paper AI and Memory Wall, Amir Gholami, Zhewei Yao, Sehoon Kim, Coleman Hooper, Michael W. Mahoney, and Kurt Keutzer report that, over the 20 years they analyzed, peak server hardware FLOPS grew by 3.0× per two years. Over the same period, DRAM bandwidth grew by 1.6× and interconnect bandwidth by 1.4× per two years. These are the authors’ historical growth rates, not forecasts or specifications for every current system.
The widening difference helps explain why memory bandwidth can dominate performance, particularly in AI serving. But it does not mean every AI task is memory-bound: the limiting factor depends on the workload and system. A model can fit on one device and still be held back by how quickly data reaches its compute units; splitting work across devices can introduce additional communication costs.
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Where the bottleneck can appear
Within a chip
Data moves through a memory hierarchy rather than appearing directly at every compute unit. Transfers between levels can limit how quickly an accelerator is kept busy, even when the model fits in the device’s memory.
Between a processor and memory
External memory may have enough capacity to hold a workload but still supply data too slowly for the processor’s peak arithmetic rate. High-bandwidth memory is one way to bring more data to an accelerator quickly, but bandwidth alone does not guarantee a workload becomes compute-bound. Data placement and system design still matter.
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Between accelerators or memory modules
Large workloads may be distributed across multiple devices or modules. The system then has to communicate data among them. Keeping an operation close to its data can help locally, while communication across devices remains a bottleneck if the task requires substantial data exchange.
Ways architects try to reduce the wall
Increase memory bandwidth or capacity
More capacity can let a system keep more of a model or its working data available, while greater bandwidth can feed compute units faster. These address different constraints, and neither guarantees better performance if data must still travel inefficiently or if communication elsewhere is limiting the workload.
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Reduce repeated data movement
Model, system, and deployment choices can aim to keep useful data local or avoid unnecessary transfers. The AI and Memory Wall paper argues for redesign across model architecture, training, and deployment, but there is no universal recipe or single measured benefit that applies to every technique and workload.
Move computation closer to data
Processing-in-memory (PIM) and compute-in-memory (CIM) place some computation near or within memory, with the goal of reducing the cost of moving data to a separate processor. A 2024 survey, Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference, examines CIM approaches for LLM inference. A 2024 ACM study describes PIM as accelerating applications by moving computations to where data is stored.
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These approaches have tradeoffs. Architectures can differ in which operations they support and how programmable they are. The ACM study, Scalability Limitations of Processing-in-Memory using Real System Evaluations, also found that communication among PIM modules can limit scalability when data locality is low. Moving computation closer to data can reduce one kind of transfer without removing the need for communication across a larger system.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What IBM NorthPole illustrates—and what it does not prove
IBM describes NorthPole as an architecture that places memory and processing together on-chip. IBM Research reports 13 terabytes per second of on-chip memory bandwidth for the design. That is a vendor-reported architecture figure, not a like-for-like benchmark against every GPU or accelerator.
For an LLM demonstration, IBM reports mapping a 3-billion-parameter Granite model across 16 cards, with 4-bit weights and activations; IBM says little data needed to move from card to card in that pipeline. These details describe IBM’s reported demonstration setup, not an independent comparative benchmark or a guarantee of performance on other models and workloads. See IBM Research’s NorthPole account.
How to compare memory-wall approaches
No single architecture is best for every AI workload. A useful comparison asks how each system handles the parts of the memory wall that matter for the intended workload:
- Capacity and bandwidth: Can the system store the working set, and how quickly can it supply the data?
- Data movement and locality: How much data must move, and how far does it travel before it reaches computation?
- Supported operations and programmability: Can the architecture efficiently run the required operations, and how readily can software use it?
- Scaling communication: What happens to data exchange costs as work spreads across devices or memory modules?
- Workload fit, cost, and maturity: Does the approach suit the actual task and deployment constraints?
The available examples establish these as important considerations, but do not support a current product ranking or a universal hardware recommendation.
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