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Averant announced three workflow advances for Solidify 5.0 on May 31, 2007: verification management that retained earlier runs, hierarchical verification that carried properties and assumptions between design levels, and a Coverage Expansion engine for formal bug hunting. The same announcement included language-support and performance claims; those should be read as claims reported at the time, not as independently reproduced results.
What advances did Averant claim in formal verification?
In its May 31, 2007 report on Averant’s release, EE Times described Solidify 5.0 as a formal property-verification tool and highlighted three additions:
- Verification management: The tool preserved previous runs so properties already proved would not need to be proved again unless the RTL changed.
- Hierarchical verification: A team could prove properties at one level of a design, then check whether those properties and their assumptions still held at the next, higher level.
- Coverage Expansion: The engine used formal methods for bug hunting, reported added coverage, and could take VCD files as starting points.
Together, these features targeted repeated work across runs and design hierarchy, while extending formal analysis into bug hunting. The report documents what the release claimed; it does not establish how the features performed across independent projects.
What did Solidify 5.0 add?
Retaining verification work
Verification management was intended to preserve the results of earlier runs. According to the EE Times account, properties that had passed did not have to be proved again unless the RTL changed. That describes the release’s stated workflow; the report does not detail how changes were detected or how results were invalidated in every case.
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Carrying checks through design hierarchy
The hierarchical flow let engineers prove properties at one level and then check that both the properties and their assumptions remained valid at a higher level. This matters because a property that holds for a component in isolation may depend on assumptions that need to be examined when that component is integrated into a larger design.
Expanding formal bug hunting
Coverage Expansion used formal engines to hunt for bugs and report added coverage. It also accepted VCD files as starting points, allowing existing waveform information to serve as an entry point for formal analysis. The 2007 report does not specify a universal coverage metric or provide an independently validated comparison against other tools.
Supporting “isunknown” and claiming a speedup
Solidify 5.0 was reported to support the “isunknown” construct in both SystemVerilog Assertions (SVA) and Property Specification Language (PSL). The release was described as the first property checker to support it; “first” is Averant’s reported claim, not an independently established historical distinction.
EE Times attributed a 3.9× speedup on a four-CPU Linux workstation to Larry Lapides, then Averant’s vice president of worldwide sales. The report does not supply enough benchmark detail to generalize that number to other designs, configurations, or workloads.
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How does formal verification differ from simulation?
Formal verification reasons about a design mathematically against stated properties or relationships. In Averant’s own taxonomy, model checking analyzes whether a design satisfies specified properties, while equivalence checking compares two designs against a reference. Averant describes Solidify’s static functional verification as another property-verification approach. These distinctions come from Averant’s company-authored white paper, not an independent comparison of methods.
Simulation executes a design with selected inputs and observes the resulting behavior; it can explore many scenarios but does not, by itself, prove that a property holds for all possible behaviors. Formal property checking instead attempts to prove stated properties or find counterexamples within the modeled conditions. The usefulness of either result depends on the design model, properties, assumptions, and tool configuration. Solidify 5.0’s claimed hierarchical flow explicitly addressed the relationship between properties and assumptions as a design moved up a hierarchy.
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What was Solidify, and where did it fit in Averant’s suite?
Averant describes Solidify as a formal verification engine for property checking, with multiple internal engines, code coverage, testbenchless bug hunting, hierarchical verification, and debug tracing. Its Solidify product page lists Verilog, VHDL, SystemVerilog, and mixed-language designs, as well as SVA, PSL, OVA, OVL, and HPL property languages. It also lists property analysis, debug traces, waveforms, testbench and monitor generation, cross-translation, and coverage reporting. These are company product descriptions, not independently tested capabilities.
Solidify was one of several products Averant described for different verification tasks:
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| Product | Averant’s stated role |
|---|---|
| Solidify | Property verification and formal analysis |
| SolidSEC | Sequential equivalence checking after modifications such as power optimization |
| SolidAC | Automatic checks for design issues such as clock-domain crossings, deadlock, and dead code |
| SolidTC | Checking false-path and multi-path constraints in SDC timing-exception files |
The descriptions in this table reflect Averant’s product summary; they are not a claim that every product was included in Solidify 5.0.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Are Averant’s speed and coverage claims independently verified?
The cited contemporaneous account reports the 3.9× workstation speedup as a statement attributed to an Averant executive. It does not present an independent benchmark, reproducible test setup, or results across multiple designs. The Coverage Expansion description likewise reports added coverage but supplies no neutral measurement establishing its scale or comparative advantage. The available sources therefore support describing these as historical vendor claims, not independently validated performance findings. That evidence limit does not show that the claims were false.
What is known about Solidify today?
Averant’s homepage lists a “Averant Ships Solidify 8.0: New GUI, Debug & Documentation Improvements” item dated June 6, 2025, and a Solidify 8.0 GUI announcement dated December 9, 2024. The company’s news index also lists self-paced training. These dated listings show that Averant announced Solidify 8.0, but they do not establish current availability, pricing, supported platforms, or whether training enrollment is open.
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