APIO gives you a shared way to coordinate an open-source FPGA workflow, but it is not a synthesis or place-and-route tool by itself. Here’s how the Hackaday Tang Nano 20K example uses APIO for Verilog checks, simulation and programming—and where GOWIN’s tools may still be the better fit.
What APIO does—and what it does not
APIO is an aggregator for FPGA toolchain projects, not a single tool that handles every stage. Al Williams describes it as “an aggregator of toolchain projects” and notes that APIO itself “doesn’t do the Verilog synthesis or place and route.” Instead, it coordinates other programs, including tools such as Yosys and GTKWave, behind a shared workflow for supported boards. Hackaday’s October 5, 2026, walkthrough uses a Sipeed Tang Nano 20K as its example.
That distinction matters when comparing APIO with GOWIN’s software. The comparison is between workflows and the tools they bring together—not between two equivalent synthesis engines. APIO’s value is a consistent route through editing checks, builds, simulation and programming; the programs it calls do the underlying work.
Set up the Tang Nano 20K project
APIO can be installed from the command line or through a Visual Studio Code extension, as described in the Hackaday example. For the board-specific project, the minimal configuration identifies APIO’s supported board ID and the design’s top-level module:
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
#1 Best Overall
- [FPGA Chip] Sipeed Tang Nano 20K employs the GW2AR-18 QN88 FPGA chip, featuring 20,736 LUT4 logic units and 15,552 registers. It incorporates two internal PLLs and multiple DSP units supporting 18-bit x 18-bit multiplication for accelerated digital computation.
- [Onboard Debugger] The BL616 chip on the Sipeed Tang Nano 20K development board provides JTAG download functionality for the FPGA, USB-to-serial communication with the FPGA, a virtual serial port for FPGA SPI communication, and a virtual serial port to control the MS5351 clock output.
- [RISC-V Linux] Sipeed Tang Nano 20K development board runs the RISC-V Linux system, enabling seamless retro gaming experiences with nano tang.
- [Application Scenarios] Sipeed Tang Nano 20K development board supports game console emulation, RGB display control, multi-screen output, 20K LUT4, and RISC-V soft core experimentation.
- [Support] "wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html".
[env:default]
board = sipeed-tang-nano-20k
top-module = ledThe exact configuration syntax and available settings can vary with APIO versions, so consult the APIO supported-boards documentation and the documentation for the version you install. APIO lists sipeed-tang-nano-20k for the Tang Nano 20K, which uses the GW2AR-LV18QN88C8/I7 FPGA.
Sipeed specifies the board with 20,736 LUT4 logic units, 15,552 flip-flops and a 27 MHz crystal. Those are manufacturer specifications, not measurements of a design’s performance. The board also has an onboard BL616 debugger, external flash, six LEDs, user buttons and display connections. See Sipeed’s Tang Nano 20K documentation for the board’s resources and specifications.
Rank #2
- [FPGA Chip] Sipeed Tang Nano 20K employs the GW2AR-18 QN88 FPGA chip, featuring 20,736 LUT4 logic units and 15,552 registers. It incorporates two internal PLLs and multiple DSP units supporting 18-bit x 18-bit multiplication for accelerated digital computation.
- [Onboard Debugger] The BL616 chip on the Sipeed Tang Nano 20K development board provides JTAG download functionality for the FPGA, USB-to-serial communication with the FPGA, a virtual serial port for FPGA SPI communication, and a virtual serial port to control the MS5351 clock output.
- [RISC-V Linux] Sipeed Tang Nano 20K development board runs the RISC-V Linux system, enabling seamless retro gaming experiences with nano tang.
- [Application Scenarios] Sipeed Tang Nano 20K development board supports game console emulation, RGB display control, multi-screen output, 20K LUT4, and RISC-V soft core experimentation.
- [Support] "wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html".
Use the open workflow for checks and simulation
Format and lint Verilog
The Hackaday example highlights formatting and linting as useful parts of an open workflow. These checks can catch style problems and likely mistakes before synthesis; they do not establish that a design will synthesize correctly or behave as intended in hardware.
Build with the selected toolchain
When you ask APIO to build, it coordinates the configured tools for the selected board and project. Yosys and other components perform the synthesis work; APIO is the workflow layer. A successful build is a step toward programming the FPGA, not proof that the design will work on the physical board.
Rank #3
- [FPGA Chip] Sipeed Tang Nano 20K employs the GW2AR-18 QN88 FPGA chip, featuring 20,736 LUT4 logic units and 15,552 registers. It incorporates two internal PLLs and multiple DSP units supporting 18-bit x 18-bit multiplication for accelerated digital computation.
- [Onboard Debugger] The BL616 chip on the Sipeed Tang Nano 20K development board provides JTAG download functionality for the FPGA, USB-to-serial communication with the FPGA, a virtual serial port for FPGA SPI communication, and a virtual serial port to control the MS5351 clock output.
- [RISC-V Linux] Sipeed Tang Nano 20K development board runs the RISC-V Linux system, enabling seamless retro gaming experiences with nano tang.
- [Application Scenarios] Sipeed Tang Nano 20K development board supports game console emulation, RGB display control, multi-screen output, 20K LUT4, and RISC-V soft core experimentation.
- [Support] "wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html".
Run a Verilog testbench and inspect its waveform
Simulation lets a testbench drive a design under controlled conditions before deployment. In the article’s example, the testbench filename follows an _tb.v suffix convention. Its simulated clock is set to 10 Hz with a one-second interval; the testbench toggles the clock every 50 ms, pulses reset and emits waveform data for GTKWave.
Those settings belong to this demonstration, not to Verilog simulation in general. The article says APIO expects $dumpvars and handles $dumpfile in its workflow; check the behavior of your installed APIO and simulator before adopting that convention. GTKWave displays the generated signals so you can inspect timing and state changes. Simulation can reveal behavioral problems before hardware deployment, but it cannot replace testing on the board or validate real electrical timing and connections.
Rank #4
- [FPGA Chip] GW2AR-18 QN88 FPGA Chip containing 20736 LUT4 logic cells and 15552 Filp-Flops.There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication
- [Onboard Debugger ] Sipeed Tang Nano 20K Development Board support JTAG for FPGA, USB to UART for FPGA,USB to SPI for FPGA communication, Control MS5351 generate frequency
- [USB2.0 HS interface] The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides mutiple clocks.Support Serial communication, high-speed SPI reception.
- [Application scenarios] Tang Nano 20K Open source Development Board supports game console emulators, drives RGB screens, multiple display outputs, 20K LUT4, RISC-V soft-core experiments.
- [Wiki] "dl.sipeed.com/shareURL/TANG/Nano_20K/1_Datasheet";Any after-Sales Privems, Please Contact us by click "Waypondev" store and ask a question or leave the message in our forum by "forum.youyeetoo .com/".
Program SRAM or external flash
The Hackaday configuration uses SRAM as its default programming target and adds a separate flash environment. Its example command for the latter is apio upload --env flash. Treat these as the author’s demonstrated configuration and command, and verify that your installed APIO and OpenFPGALoader versions support the board and options you use.
The Tang Nano 20K has external flash, and OpenFPGALoader lists the board as tangnano20k with both SRAM and external-flash support. Those are board-programming capabilities; the APIO board ID and OpenFPGALoader board flag are different identifiers used by different tools. See the OpenFPGALoader board list and Sipeed’s Linux flashing instructions. Sipeed cautions that an older Ubuntu package may not support the 20K and recommends compiling current source for newer board support, so check your installed version rather than assuming a packaged loader is current.
Recommended Free Tools
Best Value
- Package: Tang Nano 20K(Welding pins)*1 + Type-C Cabble*1
APIO versus GOWIN tools: choose by workflow needs
The Hackaday article presents practical tradeoffs, not a controlled comparison. It reports no benchmark, timing results or resource-use comparison that would show one synthesis option winning for a particular design.
| Decision area | Open workflow with APIO | GOWIN tools, as described in the article |
|---|---|---|
| Verilog checks | Formatting and linting are highlighted. | The article does not make the same specific claim. |
| Simulation | Coordinates an open simulation workflow, with GTKWave for waveform viewing. | The article describes concerns with the simulator in its setup; availability may change. |
| Vendor IP | Integrating vendor IP may be difficult. | Vendor IP blocks are a stated strength. |
| Runtime inspection | Open alternatives exist, but the article considers them less neat. | Integrated logic-analyzer capability is highlighted. |
| Pin constraints | Text files or a spreadsheet/editor extension are options. | A graphical constraints editor is highlighted. |
| Synthesis quality | No winner established; no controlled comparison is reported. | No winner established; no controlled comparison is reported. |
Choose according to what your design needs: development speed, resource use, device-specific features, vendor IP integration, runtime debugging and how you prefer to manage pin constraints. The available evidence does not establish which synthesis option produces a better result for a given design; answering that requires comparing both workflows on the same project and criteria.
One reported installation issue
Williams reports that APIO’s bundled libreadline.so.8 caused a failure on his system and that renaming or deleting the file resolved it for him. The report does not establish the affected operating systems or APIO versions, the cause, or whether the issue remains current. It is not a general fix to apply pre-emptively: first check the error, your installed versions and current APIO guidance.
Quick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
The Tool Desk
Outbyte Driver Updater FREEFix the driver behind crashes, sound loss and screen glitchesFind Drivers →Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →
