IC resistors are usually formed from layers that also serve other roles in fabrication—most often diffusion, wells, or polysilicon. Their nominal resistance is estimated from the layer’s sheet resistance and the resistor’s length-to-width ratio, but the usable value depends on the specific process, layout, bias, and foundry model. There is no universal resistor menu or set of values: designers should use the current process design kit (PDK) for the process they are implementing.
Which IC process layers can form resistors?
A resistor in an integrated circuit is commonly patterned from an existing conductive or doped layer. The layer’s fabrication purpose does not prevent it from serving as a resistor, but its electrical properties and design limits are tied to the process.
- Diffusion: Source/drain diffusion can form a resistor body. These resistors have junctions to the surrounding semiconductor, so their bias and capacitance matter.
- Wells: A well can provide a resistor structure with properties distinct from more heavily doped diffusion.
- Polysilicon: Gate polysilicon can be used as a resistor. Some processes suppress silicide over part of a polysilicon strip to keep its resistance higher.
- Other process-specific options: Some processes offer dedicated structures or back-end metal resistors. Available options vary, and modern processes do not all retain the same traditional polysilicon structure.
These are common categories, not a guaranteed menu. The PDK identifies which resistor devices the process supports and provides their models and layout rules. Analog Devices’ chapter on resistors in IC processes and NPTEL’s CMOS process material describe diffusion, well, and polysilicon examples.
How is an IC resistor’s nominal value estimated?
For a uniform layer, the first-order estimate is:
Resistance ≈ sheet resistance × (length ÷ width)
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The length-to-width ratio is the number of squares. A square has the same nominal resistance as any other square made from the same uniform layer, regardless of its absolute dimensions. A longer, narrower strip has more squares—and therefore more resistance—than a shorter, wider strip in that layer.
This estimate is a starting point, not a substitute for the PDK model. Contacts add resistance, and width bias, end effects, and the actual device definition can change the realized value. The drawn mask dimensions may not equal the electrical dimensions: lateral diffusion can make a diffused or implanted resistor wider than drawn, while contacts can add end resistance.
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How do resistor types differ in practice?
There is no generic ranking that applies across all processes. Compare the available PDK devices using the properties that matter to the circuit:
- Resistance range and area: Sheet resistance and geometry determine how much resistance can be implemented in a given footprint.
- Absolute tolerance and matching: Process variation can shift absolute values. Similarly laid-out devices may track each other, but matching depends on geometry and layout.
- Temperature and voltage behavior: Temperature coefficient, voltage coefficient, and linearity can differ by resistor structure.
- Parasitics and frequency response: Diffused resistors have junction capacitance to the substrate; it can be nonlinear and significant in frequency-sensitive circuits. In the context described by Analog Devices, polysilicon resistor capacitance is lower than that of diffused resistors. Actual parasitic values require the process model.
- Power and self-heating: Check the device’s supported dissipation and thermal behavior rather than inferring limits from its resistance alone.
- Availability and model support: A structure is useful only if the process offers it and the PDK supplies a characterized model and applicable layout rules.
A process-specific comparison illustrates why numbers must stay tied to their source. A chapter from Johannes Kepler University’s Institute for Microelectronics lists different sheet resistances, process tolerances, matching values, and temperature coefficients for options in the named IHP SG13 process. Those values describe that process, not poly, diffusion, or IC resistors in general. The IHP SG13 comparison should be read in that process context.
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Why do bias and junctions matter for diffused resistors?
A diffused resistor must be surrounded by an opposite-doping region, with the junction biased so it remains reverse-biased. Depletion extends into the resistor and reduces its conducting cross-section, which increases its resistance. If two resistors in a divider experience different bias conditions, the change may differ between them and shift the divider ratio.
Where the process and circuit permit it, separate tubs tied to the positive end of each resistor can reduce bias-related differences. That is a layout technique to evaluate against the foundry’s rules and model, not a universal fix. Diffused-resistor junction capacitance can also affect circuit behavior, especially when frequency response matters.
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How should resistor layout support accuracy and matching?
For absolute resistance, use the PDK’s modeled device and follow its geometry and contact rules; a simple square-count calculation does not capture every layout correction. For matching between resistors, layout symmetry and shared conditions are important because devices that are physically alike and close together are more likely to track than devices with different geometries or surroundings.
- Use identical unit sections when the circuit calls for a matched ratio.
- Consider interleaving and close placement of terminals to reduce geometry and thermal-gradient effects.
- Keep the devices’ orientation and surroundings consistent where the PDK’s matching guidance calls for it.
- Check the foundry’s matching model and layout practices; these govern the expected result.
Matching and absolute accuracy are separate concerns. A pair can track while both differ from a desired nominal value because of process variation. The relevant matching and tolerance figures must come from the specific process documentation.
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What should you check in the PDK before choosing a resistor?
- Identify the resistor devices actually offered by the exact process and process option you are using.
- Read the device model and design rules for sheet resistance, geometry, contacts, and any layout corrections.
- Compare tolerance, matching, temperature coefficient, voltage coefficient, parasitics, and supported power dissipation for the intended circuit conditions.
- For diffusion or well structures, check the required surrounding-region bias and the modeled junction effects.
- Use the PDK’s layout and matching guidance, then verify the resulting design with the supported simulation and verification flow.
Educational process examples are not substitutes for these specifications. For example, Georgia Institute of Technology’s Spring 2020 teaching page gives example pre-deposition conditions of 890 °C for 14 minutes for P-well, 935 °C for 25 minutes for P+, and 950 °C for 90 minutes for N+. These are example parameters for that teaching process, not universal or current commercial foundry settings; the page notes diffusion’s use in forming integrated resistors as well as transistor source/drain regions and wells. Georgia Tech’s CMOS process page provides that example context.
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