Renesas’s RZ/Five is a single-core, 1.0 GHz, 64-bit RISC-V microprocessor designed for Linux-capable IoT edge devices. Its main design proposition is broader processor-architecture choice alongside integrated connectivity and analog-sensor interfaces—not a guaranteed performance or cost win. Renesas’s September 2022 white paper describes its specifications, evaluation setup, and potential migration benefits, but does not provide independent benchmarks or quantified savings.
What RZ/Five changes for an IoT edge design
RZ/Five is a general-purpose MPU from Renesas Electronics built around the open RISC-V instruction set architecture (ISA). Its CPU is Andes Technology’s AX45MP: one 64-bit core running at 1.0 GHz. Renesas positions the processor for edge systems that need Linux-class processing, network connectivity, and acquisition of analog sensor data.
The open ISA gives product teams another architecture to evaluate alongside Arm-based options. Renesas’s white paper presents architecture choice as a way to reduce some proprietary or geopolitical supply risks. That is a rationale for considering RISC-V, not a promise of uninterrupted component supply.
Which interfaces and memory does Renesas specify?
The September 2022 white paper lists the following RZ/Five capabilities. Ethernet channel count varies by package, so check the current datasheet and exact part before fixing a board design.
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| Area | Specification in the white paper |
|---|---|
| CPU | Single-core, 64-bit Andes AX45MP RISC-V CPU at 1.0 GHz |
| Internal memory | 128 KB RAM with ECC |
| External memory interface | 16-bit DDR3L/DDR4 interface with ECC |
| Packages | 361-pin or 266-pin PBGA; Ethernet channel count differs by package |
| Networking and industrial interfaces | Gigabit Ethernet and two CAN-FD channels |
| USB and storage | USB 2.0 host and host/function ports; two SDHI/UHS-I/MMC interfaces |
| Serial and peripheral interfaces | SPI multi-I/O; four I2C; two SCI; five UART; three RSPI |
| Timers and conversion | Eight 16-bit MTU timers; one watchdog timer; two 12-bit ADCs |
For an edge-device architecture, the integrated 12-bit ADCs may be relevant when sensors provide analog signals; Ethernet and CAN-FD offer different networking and control options. The listed interfaces establish possible design building blocks, not a measured workload result or proof of real-time performance.
How strong is the performance claim?
Renesas estimates the AX45MP’s performance at approximately 1.3 times that of an Arm Cortex-A53, describing it as expected performance within its class. The white paper does not state a benchmark workload, system configuration, power comparison, or measurement method. Treat the figure as a vendor estimate, not a universal or independently verified advantage.
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The paper also connects the 1 GHz CPU with sensor-data collection, analysis, and network-protocol processing. Those are intended use cases; it supplies no benchmark demonstrating how the processor performs on a particular application. A product team should compare candidate systems using its own representative software, memory configuration, and power constraints.
What does the evaluation and migration path look like?
Renesas describes an evaluation kit built around a SMARC-compliant module board containing RZ/Five and DDR memory, paired with a carrier board that exposes Ethernet, USB, CAN, and other connectors. Renesas says the same carrier environment can be used to evaluate RZ/Five and the Arm-based RZ/G2UL by changing the module board.
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The vendor also says it provides a CIP Linux Board Support Package (BSP) for each processor and that standard APIs let developers focus on application software. This is a starting point for evaluation, not a guarantee that arbitrary Arm binaries or existing board designs will transfer without engineering work.
Renesas states that RZ/Five and RZ/G2UL are pin-compatible and can use the same PCB design. That can reduce board-level changes when considering the two options, but it does not make their software, performance, or complete system behavior identical. Verify package, peripheral, and design requirements against the exact parts and documentation you intend to use.
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Questions to resolve before choosing a processor
- Can the application and required libraries be built and supported for the chosen RISC-V environment?
- Does the exact package provide the Ethernet and other interfaces the product needs?
- How does each candidate perform and consume power on the product’s actual workload?
- Who will maintain the BSP, application stack, and security updates over the product’s service life?
- What changes remain in the schematic, PCB, power design, and validation plan despite claimed pin compatibility?
What cost and long-term support benefits are established?
Renesas describes several design choices that it says could reduce cost or design effort, but the white paper reports no savings amount or comparative bill of materials.
- Using the integrated ADCs may avoid external conversion components where they meet the design’s requirements.
- Renesas describes its DA9062 PMIC as optimized for RZ/Five to simplify power design.
- A four-layer PCB is described as possible, with DDR wiring verified to JEDEC standards; Renesas says it offers a reference four-layer board design.
These are vendor-presented design options, not guaranteed savings. Whether they help depends on the board, power requirements, components, and validation work for the final product.
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The white paper says the Civil Infrastructure Platform (CIP), spearheaded by the Linux Foundation, provides a base layer for Linux-based embedded systems serving civil infrastructure needs. It states that CIP maintains industrial-grade Linux for over 10 years and that Renesas’s Verified Linux Package is based on the CIP kernel to reduce customer maintenance effort. This 2022 description does not establish a current maintenance end date or a service guarantee for a particular RZ/Five package; confirm support terms for the software release you plan to deploy.
What the white paper does—and does not—show
Renesas’s six-page paper, published in September 2022 and attributed to Takeshi Maeda of the company, makes a vendor case for expanding processor choice. It states: “As a microprocessor equipped with a 64-bit RISC-V CPU, the RZ/Five offers customers expanded CPU options as well as superior CPU performance within its class.” The performance characterization belongs to Renesas; the paper does not give the methodology needed to assess it independently.
The paper is useful for identifying the processor’s stated architecture, interfaces, evaluation approach, and possible board-design mechanisms. It does not establish present-day component availability, lifecycle status, pricing, quantified cost reduction, independent performance or power results, or guaranteed migration effort. Those points require current product documentation and project-specific evaluation.
For hardware evaluation, consult Renesas’s RZ/Five evaluation board kit information and verify current availability, included hardware, and software support with the vendor. The paper confirms the kit’s relevance to its described SMARC evaluation approach, not its present stock status or exact contents.
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