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The PLS Universal Access Device 3+ (UAD3+) is a hardware interface for debugging, tracing, profiling, calibration and testing embedded processors. It works with PLS’s Universal Debug Engine (UDE) software, which provides the debugging and analysis environment. Its published specifications include support for synchronizing as many as eight cores or targets and trace-memory capacity up to 4 GBytes, though those figures come from the product’s 2010 launch announcement.
What the UAD3+ is—and what it is not
UAD3+ is the probe hardware that connects an engineer’s host system to an embedded target. UDE is the associated software: it provides source-level and assembler-level debugging, runtime observation, system visualization, scripted test automation, in-system flash programming, RTOS support and AUTOSAR development. PLS describes UDE as a development environment for multicore systems-on-chip (SoCs) and microcontrollers.
That distinction matters when evaluating the platform. A probe’s published trace rate or memory capacity does not, by itself, establish that a particular target can use every feature. The processor, its debug and trace interfaces, the selected pod or adapter, and the UDE configuration all need to match. PLS lists UAD3+ among the access devices supported by UDE; check PLS’s current datasheet and target-specific documentation for a particular setup.
How UAD3+ helps debug multicore systems
On a complex SoC, engineers often need to relate events across processors rather than inspect a single core in isolation. PLS’s 2010 launch announcement says UAD3+ can control and synchronize up to eight cores and targets. With a compatible target and setup, synchronized control can help engineers examine how concurrent software behaves around breakpoints, stops, steps and restarts.
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UDE supplies the software workflow for inspecting source and assembler, observing runtime state and analyzing captured trace. Trace provides a record of execution activity for investigation; it complements interactive debugging rather than replacing it. Which events and processors can be observed depends on the target’s trace hardware and supported protocols.
Published trace and interface specifications
| Capability | Published figure or support | Source and qualification |
|---|---|---|
| Concurrent core and target control | Up to eight cores and targets | PLS/EE Times launch announcement, 2010; a launch-era maximum, not a guarantee for every target configuration. |
| Trace memory | Up to 4 GBytes | PLS/EE Times launch announcement, 2010. PLS’s current multicore feature documentation also describes trace memory scalable to 4 GBytes. |
| Parallel trace | Trace stream width up to 32 bits; trace signals up to 500 MHz | PLS/EE Times launch announcement, 2010. |
| High-speed serial trace | Up to four lanes at 3.125 Gbit/s per lane | PLS current multicore feature documentation; confirm the applicable pod and target configuration with PLS. |
| Pod-to-base-unit cable | Lengths up to 5 m | PLS current multicore feature documentation; configuration-dependent. |
| Debug and trace interfaces | Debug access includes JTAG, DAP and SWD; trace ecosystem includes CoreSight ETM and Nexus/AURIX-oriented protocols. | PLS/EE Times announcement, 2010, and PLS feature documentation. Support depends on the processor and interface configuration. |
The numbers describe different interface characteristics, not one interchangeable bandwidth figure. In particular, the 2010 parallel-trace figures and the current documentation’s serial-lane rate refer to different trace modes. Do not assume every maximum applies at once or is available on every target; verify the latest PLS datasheet for the exact device, pod and configuration.
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Can it test AURIX or AUTOSAR software?
AURIX and synchronized dual-MCU debugging
PLS documents a Multi AURIX adapter for debugging two tightly coupled AURIX microcontrollers in one session. Its documented functions include synchronized stop, single-step and restart, plus synchronized suspension of peripherals. This is relevant to redundant or fault-tolerant designs in which developers need coordinated control of both MCUs. The adapter is a target-specific part of the setup, not a feature to assume for every UAD3+ connection.
AUTOSAR and software testing
UDE supports AUTOSAR development and scripted test automation, alongside debugging and in-system flash programming. These software capabilities can be used as part of an embedded development and test workflow. The available functions still depend on the target, UDE setup and applicable licensing; the platform description does not establish that every AUTOSAR test is automated or that a particular compliance result is guaranteed.
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A typical UAD3+ development workflow
- Match the hardware to the target. Select a compatible debug or trace pod, interface and any required target-specific adapter. Confirm the processor and protocols in PLS’s current documentation.
- Connect the target. Attach the pod to the target’s supported debug or trace connection and connect the pod to the UAD3+ base unit. Respect the documented configuration and cable limits.
- Set up UDE. Configure the target and use UDE to load or program firmware where supported, then establish the debug session.
- Inspect execution. Set source-level or multicore breakpoints and observe runtime state using the functions available for the target.
- Capture and analyze trace. Configure supported trace sources, capture execution activity and analyze it in UDE to investigate behavior that may not be apparent from a breakpoint alone.
- Automate repeatable checks. Use UDE’s scripted test automation where appropriate, and use in-system flash programming when it fits the target workflow.
What to verify when comparing professional probes
UAD3+ is aimed at embedded systems where trace depth and coordinated visibility across cores matter. A meaningful comparison with another probe should consider more than peak bandwidth:
- Target coverage: supported processor families, debug interfaces and trace protocols for the exact device and silicon revision.
- Concurrency and synchronization: the number of cores or targets controllable together, and what synchronized operations are supported.
- Trace capacity and transport: memory depth, parallel width or serial-lane configuration, signal rate and the target’s own trace capabilities.
- Software workflow: source and assembler debugging, profiling, test automation, flash programming, scripting, and RTOS or AUTOSAR support.
- Physical setup: pod separation, cable reach, adapters and any electrical-isolation requirements for the application.
- Deployment requirements: application engineering, licensing and availability of target-specific hardware. Confirm these details with PLS or an authorized distributor for the intended region and system.
Which processor families were named at launch?
The 2010 EE Times announcement named ARM7/9/11, Cortex-M3/R4/A8, PowerArchitecture, TriCore, XC2000/XE166 and SH-2A families. This is a historical list from the launch announcement, not a complete or current compatibility list. For a present-day design, confirm exact processor and trace support in current PLS documentation rather than relying on family names alone.
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