OpenOCD connects host-side development tools to embedded hardware for source-level debugging, in-system flash programming, and—over JTAG—boundary-scan testing. It is not a universal hardware tool: what it can do depends on the adapter, transport, target, configuration, and OpenOCD build.
What is OpenOCD used for?
The OpenOCD User’s Guide says the project “aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices.” In practice, OpenOCD acts as a host-side server between development tools and a debug adapter connected to a target board. The adapter supplies the electrical signaling to the chip; OpenOCD uses the selected driver and configuration to communicate with it. OpenOCD’s project overview describes these intended uses.
A typical setup has three parts: host tools such as GDB, OpenOCD and its adapter driver, and the physical adapter connected to the board. Configuration files describe the adapter, board wiring and target details that OpenOCD needs, such as processor, reset behavior, scan chain, and flash configuration. The exact files and commands depend on the board and installed build.
What can OpenOCD do beyond breakpoints?
Debug supported embedded targets
OpenOCD can expose a GDB-facing path for debugging supported targets. That lets a developer work with program execution and source-level debugging through host tools, rather than relying only on a chip vendor’s graphical debugger. Processor support depends on the target and the OpenOCD build in use.
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- This hardware supports USB to UART and JTAG, and the voltage supports 1.8V 3.3V 5V.Support standard JTAG interface and 2-wire SWD debugging interface.
- The Jtag main control chip uses STM32F205, can not afford to lose the firmware, hardware upgrade to the latest version of V9.4, can provide 3.3V voltage of 0.8A.
- Stable and reliable chipset CP2102,Baud rates: 300 bps to 1.5 Mbps,Connect MCU easily to your computer!Standard USB type A male and TTL 5pin connector. 5pins for 3.3V, RST, TXD, RXD, GND & 5V.
- Support IAR KEIL MDK,nRF51822 nRF52810 NRF52832 JLINK V9 DA14580 JLINKV9 SDW Emulation Debugger ARM Jtag Debugger Supports MDK/IAR/KEIL. Supports debugging of all ARM chips, supports MDK or IAR, and compile environment IDE supported by other standard J*Link standards.
- Kind reminder: Our device is designed for experienced embedded engineers or enthusiasts who know how to use it. Please refer to the pictures on this webpage for instructions. We apologize for not providing any additional product user manuals!
Program flash in-system
OpenOCD can program supported internal or external flash without removing the chip from the board. Flash programming is part of the target’s debug-support stack: OpenOCD needs the right target configuration and support for the chip’s flash implementation. The guide documents specific flash families and commands; that does not establish compatibility with every device. Confirm support for the exact target in the installed version’s guide and configuration files. The adapter and target configuration guide explains the dependencies.
Run boundary-scan tests over JTAG
JTAG can support both debugging and boundary-scan testing, which can help test board connections through the chip’s boundary-scan cells. This is distinct from ordinary software debugging, and requires a JTAG-capable path and suitable target support. SWD does not provide boundary-scan capability.
Rank #2
- Compatible With full range of devices: Xilinx FPGAs, XILINX Zynq-7000, XILINX CoolRunnerTM/CoolRunner-II CPLDs, Artix7, SOC, Xilinx Platform Flash ISP configuration PROMs, Select third-party SPI PROMs, Select third-party BPI PROMs, etc. Adaptive target board I/O voltage, support 5V, 3.3V, 2.5V, 1.8V and 1.5V interface levels, VREF levels range from 1.4V to 5V. The measured minimum can support up to 1.2V, and an interface protection circuit is added.
- Support for new devices and new versions of software is also a future use trend. The downloader has been mass-produced and tested for a long time, and the quality is stable and reliable.
- Fast download speed: up to 30M. Speeds faster than Platform cable USB I and II generations. It is recommended to use ISE14.1 or above software with its own driver..Support impact, Chipscope, EDK, Vivado2014 and above, Including software such as Vivado2018.
- The JTAG download clock Compatible With the adaptation of XILINX software, and can also be manually selected. 6. Support all operating systems, XP, WIN7, WIN8, WIN10 system and Linux system.
- Pckage include:FPGA ProgrammmerCable*1,adapter*1,14pin cable*2,10pin cable*1,7pin cable*1,7pin dupont cable*1
What is the difference between JTAG and SWD?
| Transport | Typical role in OpenOCD | Important limitation |
|---|---|---|
| JTAG | Debugging and boundary-scan testing, where supported | Requires compatible target, adapter, wiring, and configuration |
| SWD | ARM-specific, debug-oriented transport using fewer signal wires than JTAG | Does not provide boundary-scan support |
These transports are not interchangeable in capability. Both the target and the adapter driver in your installed OpenOCD version must support the transport you choose. If you need boundary scan, an SWD-only setup will not meet that requirement. The official adapter configuration documentation covers transport selection.
What debug probe works with OpenOCD?
There is no single probe that works with every board. OpenOCD supports adapter drivers for multiple hardware families, including CMSIS-DAP, but a family’s presence in the documentation does not guarantee that every physical model, target, or operation is compatible. Check the driver and transport support in the OpenOCD build you intend to use, then match the probe to the board electrically and mechanically.
Rank #3
- USB to FPGA Interface: The USB Blaster Download Cable interfaces a USB port on a host computer to an Altera FPGA mounted on a printed circuit board
- Configuration Data Transfer: The cable sends configuration data from the PC to a standard 10-pin header connected to the FPGA
- Versatile Programming Applications: You can use the USB Blaster cable to iteratively download configuration data to a system during prototyping or to program data into the system during production
- Comprehensive Device Support: Supports most of the ALTERA FPGA/CPLD devices, Active Serial Configuration devices, Enhanced Configuration devices, and supports AS, PS, JTAG three download modes
- High-Speed Design Architecture: Features high-speed, stable performance with internal FT245R+CPLD design for efficient programming and debugging operations
- Transport: Confirm the probe and target both support JTAG, SWD, or the other required transport.
- Voltage and signals: Check target signal voltage, adapter tolerance or level conversion, ground, and whether reset signals are needed.
- Connector and pinout: Compare the board header with the probe cable; a pinout-changing cable or jumper wires may be necessary.
- Clocking: Determine whether the setup needs adaptive clocking and whether the probe supports it.
- Host connection and driver: Verify the probe’s host interface and that your OpenOCD build includes its driver.
A CMSIS-DAP JTAG/SWD probe is one category to investigate, not a tested product recommendation. A level converter or wiring changes may also be required for a particular board. The hardware guide and adapter configuration guide help identify the relevant checks.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How do I configure OpenOCD for my board?
OpenOCD’s project setup guide groups common configuration into interface, board, and target files. Interface configuration selects the adapter and transport; board configuration captures board-specific wiring or setup; target configuration describes the chip and, where needed, its memory and flash. Existing files can be enough for a straightforward supported board. Unusual wiring, external memory, or a new chip can require additions or new target support.
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- Category:XILINX FPGA/CPLD configuration and programming Cable
- Software:Xilinx ISE, iMPACT, ChipScope
- Interfaces:JTAG, Slave-Serial and SPI
- Solution:CY7C68013A+XC2C256
- User Guide CD?schematic,software, drivers and examples
- Identify the exact hardware. Record the board revision, processor, debug connector pinout, target signal voltage, and the transport supported by both target and probe.
- Check the installed OpenOCD build. Confirm it includes the needed adapter driver and target support; do not assume the current online guide matches an older installed build.
- Find the relevant configuration files. Look for interface, board, and target configurations that match the adapter and board. Treat a similar board file as a starting point, not proof that its pinout or reset behavior matches yours.
- Review target and flash details. Verify that the processor and flash implementation are supported and that configuration reflects the actual board.
- Connect and validate the setup. Check ground, voltage compatibility, signal wiring, reset lines, and any required level conversion before attempting a debug or flash operation.
For a board that lacks a suitable configuration, expect to adapt the board-specific settings or develop target support; a working adapter alone is not enough. See OpenOCD’s project setup guide for the configuration model.
How current is the OpenOCD documentation?
The official online User’s Guide identifies itself as version 0.12.0+dev and is dated 28 September 2026. That is the guide’s stated development-version label, not evidence that a stable 0.12.0 release was made. Driver and target support can vary by installed version, so use the documentation and configuration files corresponding to the build you actually run. The guide is available at OpenOCD User’s Guide; the project mirror is at GitHub.
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