Do these 3 things before closing this tab:
1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsStart with the FPGA’s exact family and part number. For documented open-source workflows, iCE40 pairs Yosys, nextpnr, and IceStorm; ECP5 pairs Yosys, nextpnr, and Project Trellis. Gowin support is documented through Yosys, nextpnr-himbaechel, and Project Apicula for listed devices and boards. These flows are not interchangeable, and a tool listing an architecture does not necessarily mean every device, feature, or bitstream step is supported.
How to choose an open-source FPGA toolchain
FPGA tool support is architecture-specific. Before choosing software—or buying a board—record the chip’s full part number, not just the vendor or family name. Then check that the target is supported, whether support is marked experimental, whether the design uses hard IP that the flow can handle, and how the resulting bitstream will be programmed.
- Identify the exact device. Read the part marking or board documentation and note the full device identifier.
- Check the architecture and support status. Confirm that the relevant project lists the device, and distinguish established flows from targets explicitly marked experimental.
- Check design features. Look for support for the hard blocks your RTL needs, such as block RAM, PLLs, transceivers, or DSP resources. In particular, verify whether a feature can be inferred from RTL or requires manual instantiation.
- Confirm the complete route to hardware. Make sure you have synthesis, place and route, bitstream generation, and a compatible programming method—not merely a tool that can target the architecture.
- Match the setup to your host and board. Check the documented board and device identifiers, operating-system support, and any required external vendor software.
At a glance: documented toolchains and their fit
| Target or use | Documented toolchain | Support and important limits | Best fit |
|---|---|---|---|
| Lattice iCE40 | Yosys for synthesis; nextpnr for place and route; IceStorm utilities for bitstream handling | IceStorm documents LP/HX 1K, 4K, and 8K support and UltraPlus support for features including DSPs, oscillators, RGB, and SPRAM. LM, Ultra, and UltraLite are listed as not yet supported by the IceStorm page. | A project using a specifically supported iCE40 device and a fully open-source implementation and programming flow. |
| Lattice ECP5 | Yosys, nextpnr, and Project Trellis | Trellis documents support for all ECP5 devices and lists ULX3S among boards confirmed working. Its feature-status page qualifies multiplier support: manual MULT18X18D instantiation is possible, but inference and more advanced DSP features are not supported there. | An ECP5 design whose required hard-IP features match Trellis’s documented status. |
| Gowin | Yosys, nextpnr-himbaechel, Project Apicula, and openFPGALoader | Apicula documents specific supported boards and device identifiers; this is not blanket support for every Gowin part. | A listed Gowin board or part, after checking the matching device option and board-specific setup. |
| Other nextpnr architectures | Architecture-dependent; nextpnr lists several additional targets | The nextpnr README labels Cyclone V, MachXO2, and Xilinx 7-series experimental. NG-Ultra bitstream creation requires NanoXplore’s Impulse tool according to nextpnr documentation. | Only when the target’s maturity and any non-open-source step suit the project. |
| New FPGA architecture or placement-and-routing algorithms | Verilog-to-Routing (VtR) and VPR | The nextpnr FAQ describes VtR as focused on FPGA architecture and algorithm development, and describes VPR as a place-and-route tool with a research focus. This is a different goal from selecting a turnkey flow for a particular commercial chip. | Architecture and CAD research rather than a default implementation flow for a supported board. |
Lattice iCE40: Yosys, nextpnr, and IceStorm
For a supported iCE40, the documented flow uses Yosys to synthesize the HDL, nextpnr to place and route the design, and IceStorm’s utilities to handle the bitstream. The nextpnr example uses icepack to produce a binary bitstream and iceprog to upload it. The nextpnr FAQ specifically recommends Yosys and nextpnr for Verilog development on Lattice iCE40 when an open-source toolchain is needed.
Check the full part number against IceStorm’s stated coverage. Its documentation describes iCE40 LP/HX 1K, 4K, and 8K devices, plus UltraPlus support including DSPs, oscillators, RGB, and SPRAM. The same page says iCE40 LM, Ultra, and UltraLite are not yet supported. “iCE40” on a board listing by itself is therefore not enough to establish compatibility.
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Lattice ECP5: Yosys, nextpnr, and Project Trellis
Project Trellis documents a fully open-source ECP5 flow: Yosys handles Verilog synthesis, nextpnr performs place and route, and Trellis provides the device database and bitstream-generation tools. Trellis says it supports all ECP5 devices and names the ULX3S among development boards confirmed working.
Hard-IP support can determine whether the flow fits a design. Trellis’s status list includes logic slices and carries, distributed RAM, internal interconnect, basic I/O, block RAM, global networks, PLLs, and transceivers. Its multiplier qualification matters: a design can manually instantiate MULT18X18D, but multiplier inference and more advanced DSP features are not supported in the documented status. Check the project’s feature status against the way your RTL uses those resources, rather than assuming that a listed block is inferred or usable in every configuration.
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Gowin: Yosys, nextpnr-himbaechel, and Project Apicula
Project Apicula documents an open-tool flow for Gowin bitstreams. Its getting-started requirements include Yosys, nextpnr-himbaechel, openFPGALoader, and Python 3.9 or later. The examples cover synthesis, place and route, packing, and programming a board.
Apicula’s board and device list is the key compatibility check. It includes the Sipeed Tang Nano 9K with device identifier GW1NR-LV9QN88PC6/I5 and the Tang Nano 20K with GW2AR-LV18QN88C8/I7. Board names and device-family options matter in the example commands; do not assume a command for one Tang board applies to another Gowin device. Check Apicula’s current supported list and match the exact identifier before building around this flow.
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When nextpnr lists a target, check its maturity and bitstream path
The nextpnr README lists Lattice Nexus, NanoXplore NG-Ultra, and Cologne Chip GateMate alongside iCE40, ECP5, and Gowin. It labels Cyclone V, MachXO2, and Xilinx 7-series experimental. Those labels should not be treated as equivalent to the documented iCE40 and ECP5 flows: experimental support is a meaningful qualification when deciding whether a project can rely on a toolchain.
There is also a distinction between placement and routing and a complete end-to-end open flow. For NG-Ultra, nextpnr documentation says binary bitstream creation requires NanoXplore’s Impulse tool. If the requirement is that every implementation step use open-source software, that vendor-tool dependency is decisive.
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VPR and Verilog-to-Routing are for a different job
VPR and VtR are relevant when the work is about FPGA architecture or CAD algorithms, rather than simply implementing a design on a named supported board. The nextpnr FAQ describes VtR as flexible but focused on architecture and algorithm development, and characterizes VPR as a place-and-route tool with a research focus. For a project targeting a specific chip, begin with that chip’s documented implementation flow; choose VPR or VtR when their architecture-development purpose matches the work.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Installing a bundled tool distribution
OSS CAD Suite is a binary distribution that brings together tools for RTL synthesis, formal verification, place and route, programming, simulation, and testing. Its documented components include Yosys, nextpnr architecture targets, IceStorm, Trellis, Oxide, Apicula, openFPGALoader, OpenOCD, and ECP5 programming utilities. It can reduce the effort of assembling a compatible environment, but it does not make an unsupported device supported or remove architecture-specific setup.
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Check the release information for the host computer before installing. The suite lists GHDL on Linux x64 and Darwin ARM64 among platform-specific qualifications; the repository describes nightly builds and says Darwin x64 delivery is planned to stop. Confirm what the current release provides for your operating system rather than assuming every component is available on every host.
Board and programming checklist
A compatible development board is useful only when the FPGA, constraints, and programming path agree with the chosen flow. Project Trellis lists ULX3S among confirmed working boards, while Apicula lists the Sipeed Tang Nano 9K. Before buying or configuring a board, verify:
- The exact FPGA part is covered by the target project.
- The board’s constraints and pin assignments match the design.
- The documented flow can generate a bitstream for that device.
- The board can be programmed using the documented onboard interface or a separately compatible programmer.
OSS CAD Suite documents programming utilities, but the cited project documentation does not establish that a generic probe or adapter works with a particular board. Confirm the board’s interface and required hardware before purchasing a separate programmer.
There is no universal fastest or best flow
The cited project documentation does not establish a universal performance winner. A practical choice depends on exact device coverage, support maturity, the design’s hard-IP requirements, programming, and host setup. For a specifically supported iCE40 or ECP5, the documented flows provide clear starting points; Gowin users should confirm Apicula’s exact board and part listing; experimental targets and research-focused tools need a closer fit assessment.
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