NEC’s 0.15-micron ASIC story was a system-on-chip platform announcement, not a clearly documented standalone “ASIC core” product. In March 1999, EE Times reported that NEC planned to accept designs for its CB-11 platform beginning in June, with production targeted for the first quarter of 2000. CB-11 was designed for 0.18- and 0.15-micron processes and aimed at multimedia SoCs. Those dates were announced targets, not confirmation that the milestones occurred as planned.
What NEC announced in 1999
CB-11 combined semiconductor process options with standard-cell libraries and intellectual property (IP) cores, giving customers building blocks for custom system-on-chip designs. The announcement described a platform for integrating functions on a chip; it did not establish that NEC was selling a standalone retail product called an “ASIC core.”
NEC planned to start taking customer designs in June 1999 and targeted production for the first quarter of 2000. The available announcement documents the plan, not whether each milestone was met. It positioned CB-11 for multimedia applications and specified support for 0.18- and 0.15-micron processes.
CB-11’s reported integration capabilities
EE Times described CB-11 as able to combine logic with a range of memory and circuit modules. The figures below are capabilities reported for the platform in 1999, not proof that every combination or maximum was achieved in commercial chips.
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| Capability | What the 1999 report said |
|---|---|
| Gate capacity | Up to 34 million gates |
| I/O capacity | Up to 2,700 pins |
| Interconnect | Five, six or seven layers |
| Integration options | DRAM, flash, analog, CMOS and high-speed BiCMOS modules |
The combination was the point of the SoC pitch: customers could integrate more system functions into a custom chip rather than assemble them from separate components. The report lists platform options; it does not say that every design could use every module at once.
Why the announcement mattered to NEC
EE Times framed CB-11 as part of NEC’s effort to regain ground in the ASIC market and expand its system-on-chip business, with a focus on customers in the United States. The article reported NEC ASIC revenue of $1.23 billion in 1998, down from $1.78 billion in 1997, and said Lucent had taken the lead as the largest ASIC producer in 1998. These are the contemporary trade publication’s historical figures and market characterization.
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How CB-12 relates to the 0.15-micron story
NEC’s later technical documentation identifies CB-12 as its 0.15-micron-centered ASIC lineup. A 2006 NEC Technical Journal review says CB-12 was compatible with the CB130 0.13-micron and CB90 90nm generations, as well as more advanced processors then in development. The review also describes NEC’s V850E CPU core and licensed ARM7, ARM9 and ARM11 family cores for ASIC use.
That later lineup makes “ASIC cores” understandable as a reference to embedded CPU IP available within ASIC designs, but it should not be confused with the 1999 CB-11 platform announcement. NEC’s technical review also mentions associated Embedded Trace Macrocell and Vector Floating-Point Processor IP, along with a secondary linked cache controller; these are components of the documented IP range, not evidence that every CB-12 design included them.
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A 2002 HPCwire report described networking technology demonstrations involving CB-11 and CB-12. It also reported a switch-fabric solution that NEC developed with Erlang Technology for enterprise and carrier-class OEMs. This documents a demonstration and collaboration, not a record of customer shipments.
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What the record does—and does not—establish
- CB-11 was announced as an SoC ASIC platform for 0.18- and 0.15-micron processes, with design acceptance planned for June 1999 and production targeted for early 2000.
- Its gate, I/O and interconnect figures were reported platform maxima, not independently corroborated shipment specifications.
- NEC’s later documentation identifies CB-12 as a 0.15-micron lineup and describes embedded CPU and related IP options.
- The sources establish a later networking demonstration, but do not establish first-hand chip testing, fulfillment of the original production target, or present-day availability.
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