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What compression ratio measures
For on-chip scan compression, the compression ratio is the number of internally balanced scan chains divided by the number of scan channels (pairs of scan I/O pins). For example, 100 internal chains and 10 scan channels produce a 10:1, or 10x, ratio. This is the independent axis for comparing runs: measure the other performance outcomes at each ratio rather than treating a larger ratio as proof of better performance. EE Times’ 2007 explanation uses this definition.
A fair comparison should hold the design, fault list, and ATPG constraints/settings constant. Where possible, use one common fault list across tools; differences in fault accounting can otherwise make coverage results appear better or worse without reflecting a real change in test quality.
Establish an uncompressed baseline
Begin with an uncompressed transition-delay test. Record the testable fault coverage and baseline ATPG pattern count. In this method, testable fault coverage is detected faults divided by detectable faults in the uncollapsed fault list. Use that same list and the same ATPG constraints/settings for the compressed runs so coverage loss is measured against an equivalent baseline.
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Also record the uncompressed tester-cycle count. It matters because two systems with identical compression behavior can yield different practical results if one starts with a much larger baseline pattern count.
Measure coverage retention and pattern inflation at each ratio
- Run ATPG on the same design at several compression ratios with identical constraints and settings.
- For each run, record the ratio, detected and detectable faults under the common accounting method, achieved coverage, and ATPG pattern count.
- Compare each compressed run’s coverage with the uncompressed baseline. Report any loss explicitly; do not compare pattern counts as though they reached the same target if coverage differs.
- Calculate pattern inflation relative to the uncompressed pattern count at the matched coverage target. Track how that rate changes with ratio.
Pattern inflation depends on both the design and the tool, especially when unknown logic is present. Plot pattern count against compression ratio and inspect the curve; the cited method expects a fairly linear relationship with a relatively small slope, but this is a behavior to measure, not assume. A steepening curve or a higher inflation rate can consume the apparent benefit of adding scan channels.
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Use tester cycles as the practical runtime metric
Tester-cycle count is more useful than compression ratio alone because it reflects the uncompressed pattern count, pattern inflation, scan-flop count, scan-channel count, and compression ratio together. Compare complete compression-plus-ATPG systems, not just the compression hardware in isolation.
Calculate TATR as uncompressed tester cycles divided by compressed tester cycles. It is useful as a summary, but it can mislead when considered alone: a high reduction can hide poor coverage or a high baseline pattern count. Read it alongside the coverage and cycle-count figures. The EE Times article describes its cited tester-cycle expression as accurate to within 1% under that article’s assumptions; that precision should not be generalized beyond those assumptions.
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The article’s example says a 1% pattern-inflation rate puts the limiting TATR near 100x, the reciprocal of the inflation rate. Treat this as an upper-limit illustration, not a promised result: actual performance depends on the design, baseline, and implementation.
Account for physical overhead and total test cost
Compression can save tester time while increasing silicon area, routing congestion, or timing pressure. Measure area and physical effects from implementation results where available. If physical data is unavailable, record Design Compiler library-area units for each run and label them as library-area measurements rather than physical implementation results.
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Then evaluate total test cost across compression ratios, including tester-time savings and the added silicon and routing costs. Plot cost against ratio and select the cost minimum. At high ratios, incremental silicon and routing expense can exceed the value of shorter testing, so the maximum ratio is not necessarily the economical choice.
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Keep one row per tool and compression ratio, and include the baseline needed to interpret each result. A useful report contains:
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- Compression ratio, with internal-chain and channel counts.
- Uncompressed baseline coverage, pattern count, and tester cycles.
- Coverage at the same target and the coverage difference from baseline.
- Pattern count and inflation rate at that target.
- Compressed tester cycles and TATR.
- Area overhead, routing congestion, and timing impact, with the measurement basis stated.
- Total test cost and the ratio where that cost reaches its minimum.
This keeps the decision grounded in equivalent coverage and realized cost: use ratio to define the experiment, pattern inflation and cycles to assess test time, and implementation data to check whether the time saved is worth the physical expense.
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