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What is the latest Lattice FPGA with post-quantum cryptography?
It is the Lattice Mach-N2 family. Lattice announced Mach-N2 on September 16, 2026, positioning it for system control and security in infrastructure systems. The company says devices are available to order and that samples have shipped to compute and communications customers. The announcement does not give public pricing, a complete device-by-device specification table, evaluation-board details, or named distributor inventory.
Mach-N2 is built on Lattice’s Nexus 2 platform and combines integrated flash with a hardware root of trust, according to the company. Lattice also announced design support through Lattice Radiant software and its newly released Lattice Prompt AI design tool.
What does crypto-agile mean for an FPGA?
In Lattice’s description of Mach-N2, crypto agility means cryptographic algorithms can be updated in the field, with anti-rollback protection intended to prevent a device from reverting to an earlier algorithm or configuration. That matters for infrastructure expected to remain in service as security requirements change: an updateable design can accommodate newer cryptography without relying solely on fixed, unchangeable algorithms. The announcement does not detail the update process, authorization controls, or anti-rollback implementation.
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The Mach-N2 announcement also names PUF-derived device identity, DICE and SPDM attestation, configurable anti-tamper responses, and runtime APIs for AES-256-GCM, ECC 521-bit, and RSA 4096-bit. Lattice says the on-chip non-volatile flash blocks external access to the configuration bitstream and User Flash Memory. These implementation descriptions are vendor claims rather than independently verified findings.
Which cryptographic algorithms does Lattice Mach-N2 support?
Lattice lists the following algorithms and purposes for Mach-N2:
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| Purpose | Algorithms named by Lattice |
|---|---|
| Authentication and digital signatures | ML-DSA, LMS, and XMSS |
| Key exchange | ML-KEM |
| Runtime cryptographic APIs | AES-256-GCM, ECC 521-bit, and RSA 4096-bit |
The company describes the post-quantum cryptography (PQC) capabilities as CNSA 2.0-compliant. The reviewed announcements do not include independent compliance validation, so this should be read as Lattice’s characterization, not as a separately confirmed certification.
What system-control features and performance figures did Lattice announce?
Lattice targets Mach-N2 at secure system control, power sequencing, and system management. Its announcement names PCIe 4.0, 10G Ethernet, and SERDES speeds of up to 16 Gbps. It also claims up to 2x greater logic density for system-control functions, but does not identify the comparison baseline or provide a complete set of device specifications. The figures below are claims from Lattice’s September 16, 2026 announcement, not independent benchmarks.
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| Claim | Qualification |
|---|---|
| Up to 2x greater logic density | Lattice’s claim for system-control functions; the comparison baseline is not stated. |
| SERDES up to 16 Gbps | Maximum stated in the Lattice announcement; device-specific details are not provided there. |
| Configuration in under 30 milliseconds | Lattice’s stated time for a 220k system logic cell device. |
| Up to three configuration images | Lattice says primary, secondary, and golden images may be stored for fault recovery. |
Lattice also describes low-latency deterministic monitoring. The announcement does not provide a measurement or test conditions for that description.
How does Mach-N2 fit into Lattice’s secure-control FPGA portfolio?
Mach-N2 extends a secure-control and crypto-agility theme that Lattice had already announced in other FPGA families. These earlier products provide portfolio context, but their feature lists should not be treated as interchangeable with Mach-N2’s.
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- MachXO5-NX TDQ: In October 2025, Lattice described this family as supporting CNSA 2.0-compliant PQC, including LMS, XMSS, ML-DSA, ML-KEM, AES-256-GCM, SHA2, SHA3, and SHAKE. The announcement also described field algorithm updates with anti-rollback, key management, and hardware root-of-trust features.
- MachXO5D-NX: In June 2024, Lattice announced secure-control FPGAs with crypto-agile algorithms, integrated flash, a hardware root of trust, and fail-safe remote field updates. That announcement also described the Lattice Sentry stack for FPGA-based platform firmware resiliency.
Those announcements establish that Lattice’s secure-control and crypto-agility positioning predates Mach-N2; they do not confirm that every algorithm or implementation detail from another family applies to Mach-N2.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Is the Lattice Mach-N2 available to order?
Lattice said Mach-N2 devices were available for order on September 16, 2026, and that samples had shipped to customers in compute and communications. The announcement does not identify exact SKUs, prices, evaluation boards, or distributors with inventory. Confirm the specific device and current supply directly with Lattice or an authorized seller before planning a design around availability.
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What should engineers verify before choosing Mach-N2?
The announcement establishes the product’s intended role and the capabilities Lattice says it offers, but it does not provide enough detail to make a like-for-like selection or ranking against other secure-control FPGAs. Before committing to a design, request device-level documentation and verify:
Quick Recap
- Exact SKU, logic capacity, I/O, and SERDES configuration for the intended design.
- Which algorithms are implemented on the chosen device, and how field updates, signing, key management, and anti-rollback are handled.
- Boot, key-storage, attestation, and tamper-response behavior, including the relevant integration documentation.
- Power, configuration timing, and fault-recovery behavior under the system’s operating conditions.
- Availability, lifecycle support, design-tool compatibility, and the cost of evaluation and integration.
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