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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteThe headline “Intel, RISC-V Rally Rival Groups” refers to two efforts announced around March 2019: Compute Express Link (CXL), an Intel-initiated chip-to-chip interconnect, and CHIPS Alliance, a Linux Foundation project for open hardware IP and tools based on the RISC-V instruction set architecture. They were parallel ecosystem efforts, not direct competitors at the same technical layer. The 2019 membership details below are historical, not current rosters.
What were the rival groups?
Compute Express Link focused on connections between chips
Compute Express Link (CXL) was described in the March 11, 2019 EE Times report as an Intel-initiated open chip-to-chip interconnect intended to connect processors with accelerators and memory. The report named Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, and Microsoft among the other CXL members at that time.
CHIPS Alliance focused on reusable hardware IP and tools
CHIPS Alliance launched as a Linux Foundation project by RISC-V proponents. The report named Esperanto, Google, SiFive, and Western Digital as its initial members. Its goals included developing reusable blocks for embedded cores and Linux-capable multicore systems-on-chip, with an open-source design flow as a longer-term aim.
The distinction is the technical layer: CXL addressed links among chips and devices; CHIPS Alliance addressed hardware IP and tools for building systems based on an instruction set architecture (ISA). A processor could use RISC-V while also connecting to other components through an interconnect, so the two efforts were not alternatives in the sense of choosing one standard over the other.
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
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- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
Which group was CXL actually competing with?
The 2019 report identified CCIX—not CHIPS Alliance—as CXL’s direct interconnect competitor. CCIX had been launched earlier by Arm, AMD, IBM, and Xilinx. Both CXL and CCIX were described as using PCI Express as a basis and adding cache coherency, which helps connected processors and devices coordinate access to shared data.
The report relayed Intel’s claims that CXL offered lower latency and less processing overhead than CCIX, but the CXL group supplied no specific figures. Those statements are vendor-side claims reported at the time, not independently measured comparative results. The available information does not establish a performance winner.
Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
How did Intel’s relationship with RISC-V develop?
2022: Intel joined RISC-V International
On February 7, 2022, RISC-V International announced that Intel had joined at Premier membership level. The announcement said Intel’s Bob Brennan would join its Board of Directors and Technical Steering Committee. Intel described plans to contribute to RISC-V IP and software development and to support process optimization, wafer shuttles, customer designs, development boards, and infrastructure.
RISC-V International’s announcement quoted its then-CEO Calista Redmond: “Open collaboration in RISC-V has already ignited a profound shift in the semiconductor industry, and this partnership will accelerate innovation in open computing.” This was her institutional perspective on the partnership.
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Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
Intel’s software work was described as complementary
Intel’s Project RISE article characterized its software initiative as complementary to RISC-V International’s specification work. Intel said RISE focused on upstream “last mile” software support rather than maintaining a separate distribution or specification process. It cited MultiArchUefiPkg, involving existing PCIe adapters, as an example, and listed developer tools, emulators, kernel support, virtualization, and platform firmware as collaboration areas.
2026: a committee record has a narrow meaning
A February 4, 2026 Technical Steering Committee meeting record includes “Intel no longer a member” in its changes list. That supports the limited statement that Intel was no longer a member in that committee context as recorded there. It does not establish that Intel left RISC-V International as a whole.
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
Does an open RISC-V ISA mean every RISC-V chip is open-source?
No. RISC-V International describes itself as the nonprofit home of the open-standard RISC-V ISA. It says the base ISA and ratified extensions are royalty-free, open building blocks, and that members collaborate on specifications and related groups. Companies can build either free or proprietary implementations and services on that foundation. “Open ISA” therefore describes the shared instruction-set specification; it does not mean every processor design, product, or implementation is open-source.
In its 2025 annual report, RISC-V International emphasized that a shared base and common software foundations are only part of adoption. It said vertical markets also need tuned software stacks, hardware extensions, and sustained coordination among partners. The report discusses embedded and IoT, automotive, data-center computing, space, high-performance computing, and AI as areas of activity or interest; these are the organization’s characterizations, not independently verified market forecasts.
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- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
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