Infineon said on 25 November 2025 that AMD tested its 64 Mb HYPERRAM and HYPERBUS memory-controller IP with the AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit. The reported setup uses HYPERRAM as memory for a MicroBlaze V soft-core RISC-V processor. This is a claim about one named evaluation kit, not blanket validation for all AMD FPGAs.
What was tested
Infineon’s announcement describes a combination of two components: 64 Mb HYPERRAM memory and Infineon HYPERRAM controller IP. The controller acts as the memory interface for MicroBlaze V in the reported setup. AMD’s product catalog identifies the SCU35 kit as featuring a Spartan UltraScale+ SU35P FPGA.
The announcement names the memory capacity but does not give an ordering part number. It also does not establish that every retail configuration of the kit includes HYPERRAM. Confirm the board contents and reference design for the particular kit being considered.
What the validation does—and does not—establish
The evidence is limited to testing on the AMD Spartan UltraScale+ FPGA SCU35 Evaluation Kit. It does not establish compatibility or validation across every AMD FPGA, nor does it replace verification on a different board or in a production design.
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Infineon identifies HYPERBUS as the interface. AMD product marketing director Evan Leal said the choice balanced performance and low power with modest pin usage. That is AMD’s stated design rationale, not a published benchmark: Infineon’s announcement reports no numeric throughput, latency, or power results for this configuration.
What designers should check before using it
The announcement is a useful starting point for evaluating an external-memory design, but a design-in decision depends on the specific parts and implementation. Before proceeding, verify:
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- The exact HYPERRAM part and package; the announcement does not name an ordering part number.
- Voltage, pinout, timing, and operating conditions against current memory documentation and the target FPGA’s I/O capabilities.
- Board layout and pin assignments, plus whether the evaluation kit hardware and reference design match the intended application.
- The HYPERBUS controller IP’s integration documentation and licensing requirements.
- Achievable bandwidth, latency, and power under the intended workload. The announcement supplies no measurements for these.
Infineon describes its controller package as including RTL, specifications, test materials, and memory behavioral models for host-platform integration. Its product page lists the IP package at USD 2,750; price and licensing are commercial terms that should be confirmed with Infineon before purchase.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Availability and next steps
In its 25 November 2025 announcement, Infineon said the SCU35 kit was orderable, with shipments planned to start in January 2026, and described the HYPERRAM memory and controller IP as available. That dated statement does not confirm current stock or present availability. Check with AMD, Infineon, or their authorized sellers for current status.
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For further evaluation, consult the Infineon announcement, the HYPERRAM product overview, AMD’s SCU35 Evaluation Kit catalog page, and Infineon’s HYPERBUS Memory Controller IP page.
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