To program an FPGA, describe the hardware you want in an HDL, build it for the exact FPGA on your board, then load the generated configuration image onto the device. For a first physical demo, use one board and its matching official toolchain: create a small counter-to-LED design, assign the board’s pins, check timing, implement the design, and program the FPGA.
This is not the same as writing software instructions for a CPU to execute. HDL describes hardware structure and behavior; the FPGA tools translate that description into resources on a selected device.
What you need for a first FPGA project
- An FPGA development board with a clock and at least one LED.
- The vendor’s toolchain and beginner tutorial for that exact board and FPGA family.
- A programming connection, such as an onboard USB/JTAG interface or a compatible cable. Check whether the board includes the required interface.
- Basic digital logic knowledge and familiarity with one HDL. For a first project, use Verilog, VHDL, or SystemVerilog as supported by your chosen toolchain rather than trying to learn several at once.
Board and toolchain details matter: project setup, pin constraints, programming image formats, and loading procedures vary by family and board. The Altera prerequisite guide identifies basic digital logic and basic knowledge of VHDL, Verilog HDL, SystemVerilog, or schematic entry as preparation for basic Quartus design: Altera’s Quartus design prerequisites.
Choose one board and its official toolchain
Do not mix instructions from different boards. Intel’s beginner example uses a Cyclone 10 LP kit with Quartus Prime Lite, while Digilent’s walkthrough uses an Arty board with Vivado. They illustrate the same broad workflow, but their project files, constraints, device selection, and programming steps are not interchangeable.
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When choosing a board, compare the FPGA family it uses, the quality of its official documentation and examples, onboard switches, LEDs and clock, expansion I/O, host operating-system and tool-version support, and the included programming interface. If you are considering an open-source workflow, verify support for the exact FPGA and board rather than assuming a tool supports every device.
Intel’s Cyclone 10 LP tutorial was updated in 2017 and notes that screenshots may differ across software releases. Digilent’s walkthrough also describes a legacy Vivado version in its prose despite a reported 2026 page update. Use each tutorial as a board-specific learning path, and consult current vendor documentation if your menus or supported versions differ.
Program an FPGA step by step
1. Create a project for the exact FPGA
Start a new project in the selected vendor tool and choose the exact device fitted to your board. Add your HDL source file and identify its top-level module—the module whose ports connect to the outside world. The Intel example demonstrates a Verilog top-level design with a clock input, a counter, and an LED output.
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HDL is not a list of CPU instructions. A description such as a counter with a clock input asks the tools to create hardware that updates on clock edges and drives an output. The same source can require different constraints or implementation details on a different board.
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2. Write a small design
A counter-to-LED design is a practical first target: it uses the board clock, counts clock edges, and changes an LED output so you can observe the result. Intel’s Cyclone 10 LP example uses a 50 MHz onboard oscillator and a 32-bit counter; those figures describe that tutorial’s example, not a requirement for every FPGA project.
Use the port names and logic from the example for your selected board and tool. A counter that is too narrow or changes too quickly may make an LED appear steadily on or off rather than visibly blinking, so choose counter behavior appropriate to the clock and the demonstration you want.
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3. Simulate the logic before programming
Simulation lets you check that the HDL behaves as expected before implementing it on the device. If your tool supports simulation, follow its simulation guide and use a testbench to apply a clock and any needed inputs, then inspect the outputs. Intel’s basic LED tutorial concentrates on compilation and programming; it does not teach a simulation testbench, so treat simulation as a recommended learning step rather than a step shown in that tutorial.
4. Assign board pins and set timing constraints
Your HDL port names need to be connected to the physical pins wired to the board’s clock, LED, switches, or other I/O. Use the board’s official pin table or master constraint file; do not copy pin numbers from a different board. Digilent’s Vivado walkthrough uses an XDC file to associate HDL ports with physical FPGA pins, and Intel’s example includes pin and I/O-standard assignments.
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Timing constraints tell the tool what clock and interface timing to analyze. For a clocked design, define the board clock with the correct source and frequency in the constraint format used by your tool. Intel’s Quartus tutorial uses an SDC clock definition and explains that it lets Quartus verify the design against timing requirements. A missing or incorrect clock constraint can make timing analysis uninformative or incorrect.
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5. Synthesize and implement the design
Run the tool’s build flow. Synthesis translates HDL into logic resources for the selected FPGA family. Implementation—often including fitting or place-and-route—maps those resources and their connections onto the device. The tool then performs timing analysis against the constraints you supplied.
For example, Intel’s Quartus flow includes synthesis, fitting/place-and-route, assembly, and timing analysis. Microchip’s documented flow lists synthesis, pin assignments, place and route, bitstream creation, and programming. The exact names and order displayed in your software depend on the vendor toolchain.
6. Generate and load the programming image
After implementation succeeds, the tool produces a configuration or programming image for the target device. Its file format and the way it is loaded depend on the FPGA and toolchain. In Intel’s SRAM-based Cyclone example, the programming file is a .sof: connect the kit through its USB Blaster port, detect the JTAG chain, select the file, and start programming. Other devices may use different formats or offer different temporary and persistent configuration methods; do not assume the Intel procedure applies to another board.
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7. Check the physical board
Observe the LED or other output you assigned. If it behaves as intended, you have confirmed the basic path from HDL through implementation to a physical FPGA output. For a counter-based LED demo, whether the change is visibly apparent depends on the counter behavior and the board clock.
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Check dependencies in order rather than changing HDL at random:
- Confirm the board has power and the programming connection is secure.
- Verify the project targets the exact FPGA device on the board and that the latest build completed successfully.
- Check that the intended HDL module is set as the project’s top level.
- Compare every clock, LED, switch, and other port assignment with the board-specific pin table or constraint file; confirm the required I/O standard.
- Verify that the clock constraint matches the board’s clock source and frequency and that the design uses the intended clock input.
- Check reset polarity and whether the design expects a reset signal to be asserted or released before operation.
- Confirm you loaded the programming image generated by the successful build onto the intended device.
These checks follow from the project, pin, timing, and programming dependencies in the vendor workflows; they are a troubleshooting checklist, not a guarantee that every board issue has one of these causes.
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Official walkthroughs for the two example paths
- Intel Cyclone 10 LP FPGA Board — How to Program Your First FPGA: Quartus Prime Lite, Verilog, pin assignments, SDC timing constraints, compilation, JTAG programming, and an LED check.
- Digilent’s first-project walkthrough: Vivado, board files, Verilog, and XDC constraints for its Arty board workflow.
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