RISC-V is changing IoT by giving chipmakers an open instruction-set architecture they can tailor to devices ranging from tiny sensor nodes to edge computers. It is not a single processor, and choosing it does not by itself guarantee lower power, lower cost, stronger security, or better software support. Those outcomes depend on the chip, its extensions, and the surrounding development platform.
What RISC-V is—and what “open” means
RISC-V is an instruction-set architecture (ISA): the specification that defines the instructions a processor can execute and how software communicates with it. RISC-V International maintains the standard. Companies and other implementers design processor cores and chips that follow it.
That distinction matters. RISC-V is not one chip or a single performance level. Implementations can use different processor designs, capabilities, and peripherals while sharing a compatible base ISA. The architecture is modular: designers select a base instruction set and add standard extensions or, where justified, custom ones.
“Open” describes the ISA specification and the ability to implement it; it does not mean every RISC-V chip is open-source hardware, free to manufacture, or interchangeable at the binary level. A software project still needs to check the processor’s supported extensions, profile, and platform details.
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- Flexible MCU Board: Incorporate the ESP32-C3 32-bit RISC-V chip, operating up to 160 MHz, mounted multiple development ports,
- Developer Friendly: Compatible with Arduino IDE, MicroPython, CircuitPython, PlatformIO, ESP IDF, Zephyr, Matter, ESPNow, Meshtastic, WLED, ESPHome, Home Assistant, Ubidots
- Outstanding RF performance: Complete Wi-Fi functions and Bluetooth Low Energy, while supporting communication over 100m with anFL antenna
- Elaborate Power Design: 4 working modes as low as 44 μA in deep sleep mode, while supporting lithium battery charge management
- Thumb-sized Design: 21 x 17.5mm, Seeed Studio XIAO series classic form factor
Why the architecture matters for IoT
Processors can be right-sized
IoT spans battery-powered sensors, control systems, gateways, and edge computers. These products have different requirements for compute, memory, energy use, cost, and physical size. RISC-V’s modularity gives designers latitude to select a suitable base and add capabilities for a specific workload instead of treating every device as if it needed the same processor.
RISC-V International describes this as enabling “right-sized code-efficient processors,” with a better ability to balance performance against power consumption. In practice, the relevant engineering decision is the whole platform’s balance of power, performance, price, and area—not the ISA in isolation. Custom instructions or accelerators can help a defined workload, but they also affect implementation and software portability.
One ISA family can span device classes
A manufacturer may use RISC-V designs in both a small endpoint and a more capable edge processor. That creates the possibility of reusing some tools, skills, or software across product lines. It does not make every program portable automatically: code can depend on a particular profile, extension, operating system, peripheral, or vendor implementation.
Vendor choice is an ecosystem benefit, not a guarantee
An open ISA can give product teams more potential implementation and supplier options. RISC-V International presents that choice as a way to support supply-chain resilience. Whether a particular project gains meaningful flexibility depends on available compatible chips, software support, lifecycle commitments, and the cost of qualifying another supplier.
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Rank #2
- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
RISC-V International’s 2025 annual report marked 15 years of the architecture and reported 17 new members across AI, automotive, security, software, and infrastructure. Its 2024 RVA23 announcement reported more than 4,500 organizational members across 70 countries; CEO Calista Redmond separately cited more than 16,000 engineers worldwide. These are different measures of ecosystem participation, not counts of available chips or proof of production readiness for any one IoT product.
Can RISC-V run edge AI?
Yes. RISC-V systems can support AI workloads, but the practical question is what compute the target chip provides and whether its software can use it efficiently. Depending on the implementation, a design may combine ordinary scalar processing with vector or matrix capabilities, or pair the CPU with a dedicated accelerator.
Local inference can make sense when a device needs to react quickly, combine sensor inputs locally, or avoid sending raw data away from the device. Running AI and non-AI portions of an application on a shared processor can also reduce data movement in suitable designs, which may help latency and energy use. These are workload-dependent advantages, not automatic properties of every RISC-V chip; memory capacity, accelerator support, model size, and software tooling remain decisive.
RISC-V International’s 2025 annual report points to Google Coral NPU work and Synaptics Astra SL2610 integration as examples of activity in the ecosystem. It also reproduces an Omdia forecast that global AI-processor revenue would rise by almost 50% over five years, with about one quarter of that revenue coming from edge AI. This is an attributed forecast, not a measured result for RISC-V devices.
Rank #3
- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
Is RISC-V ready for IoT?
RISC-V is already used in microcontroller-class designs, and the ecosystem includes development hardware, compilers, debuggers, emulation, and operating-system support. “Ready” still depends on the product: a small bare-metal controller, a real-time device, and a Linux-capable gateway have different requirements. Evaluate the specific chip and software platform against the intended workload and the product’s support lifetime.
Profiles improve predictability, but do not make chips identical
Profiles define a more consistent set of ISA capabilities for a class of processors, helping software developers target a known baseline. RISC-V International’s 2025 annual report says RVA23 was ratified for application-class processors at the end of 2024 and describes RVB23 as an IoT and embedded software target. The same report says a draft RVM microcontroller profile was being developed, with ratification expected in 2026. That report does not establish whether RVM has since been ratified; check RISC-V International’s ratified-specifications library for the current status.
Even when two chips support the same profile, they can differ in implementation, peripherals, memory, performance, power characteristics, and optional capabilities. The RVA23 rationale also notes that ISA extensions alone do not ensure that every implementation has the same extension set. Confirm the actual chip’s supported profile and extensions rather than assuming compatibility from the RISC-V name.
Assess the complete software platform
For an IoT product, software and support can matter as much as the CPU. Before selecting a platform, check:
Rank #4
- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
- Power and performance: Compare active and sleep power, and performance per watt, under representative workloads and operating conditions.
- Memory and acceleration: Verify available RAM and storage, and confirm that required vector, matrix, or dedicated accelerator features are present and supported by the software stack.
- Portability: Establish the target profile and extensions, then identify which code can be reused and which parts depend on vendor-specific features.
- Security: Review the chip’s security features, secure-boot support, key handling, and update mechanism. The ISA name alone does not establish the security properties of the finished product.
- Real-time behavior: For control systems, check interrupt behavior, timing guarantees, RTOS support, and whether the implementation meets the project’s determinism requirements.
- Development and maintenance: Confirm compiler, debugger, emulator, and RTOS or Linux support, along with documentation, vendor assistance, and silicon availability over the intended product lifetime.
Interpret performance claims in context
RISC-V International’s IoT page cites a vendor-reported figure of 16.8 µW/MHz/DMIPS for an Upbeat Technology and SiFive dual-core SoC, in a figure attributed to an All About Circuits report in 2025. Treat it as a claim about that specific SoC and cited context, not a general RISC-V efficiency rating or a like-for-like comparison with another chip. For a product decision, compare independently measured or otherwise well-documented results using the same workload and test conditions.
How RISC-V compares with Arm for embedded devices
RISC-V and Arm are ISA families, not individual chips. A useful comparison is between complete candidate platforms: a specific processor implementation, its peripherals and memory, software support, development tools, commercial terms, and supply commitments. The ISA alone cannot settle which option is faster, more secure, cheaper, or more power-efficient.
| Decision area | What to compare |
|---|---|
| Power and performance | Active and sleep power, performance per watt, and results on the intended workload—not general claims about either ISA. |
| Software compatibility | Supported profiles and extensions, binary portability, operating-system or RTOS support, and any reliance on vendor-specific instructions. |
| AI and data handling | Memory capacity, vector or matrix features, accelerators, supported libraries, and the amount of data movement required by the application. |
| Security and updates | Implemented security features, secure-boot chain, key management, update process, and the vendor’s maintenance commitments. |
| Real-time requirements | Interrupt and timing behavior, determinism, RTOS availability, and evidence that the exact implementation meets the system’s constraints. |
| Development ecosystem | Compiler and debugger maturity, emulation, board and SDK quality, documentation, community resources, and vendor support. |
| Commercial and supply risk | Available suppliers, product lifecycle, long-term availability, qualification effort, and the terms that apply to each implementation. |
RISC-V’s distinguishing opportunity is the open, modular ISA and the choice it can create among implementations. An Arm platform may be a better fit for a given project if its specific chip, existing software, or vendor support better meets the requirements. The engineering comparison should be made at the platform level, using the same use case and acceptance criteria.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Choosing a RISC-V development board
Start from the software and hardware you need to prove, not from the ISA label. A board intended for an application-class Linux project is not automatically suitable for evaluating a tiny microcontroller, and an FPGA development kit may involve a different workflow from a fixed-function SoC board.
Best Value
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
- Define the target: Decide whether you need a microcontroller, real-time processor, Linux-capable application processor, FPGA-based system, or an edge-AI platform.
- Check the exact processor: Confirm the board’s core, supported profile and extensions, memory, peripherals, and any required accelerator.
- Inspect the software path: Verify that the board supports the needed compiler, SDK, debugger, emulator, and operating system or RTOS. Check the board’s current documentation for setup steps and known limitations.
- Plan for production relevance: If the board is for a commercial prototype, check whether the target silicon is available as a product, how the vendor supports it, and what lifecycle or supply information is offered.
One concrete example is Microchip’s Mi-V ecosystem. Its offerings span PolarFire FPGAs and SoCs, PIC64 microprocessors and PIC64-HPSC, and describe Linux, real-time, and bare-metal execution in one system. The ecosystem page lists a 64-bit quad-core RISC-V PolarFire SoC MPU, PIC64 families, RV32 soft CPUs for several FPGAs, GCC, debugging, Renode emulation, and an Icicle Development Kit training path. That makes it an example of a broader development platform—silicon, software, tools, and hardware—not a recommendation for every IoT project.
What to expect from RISC-V in IoT
RISC-V’s effect on IoT is chiefly about architectural choice: designers can build processors for a wide range of device classes and, where worthwhile, extend them for specialized work. Standards and profiles are helping define clearer software targets, while boards, toolchains, operating systems, emulators, and vendor support determine how quickly a team can turn that flexibility into a product.
For a project decision, treat RISC-V as a platform candidate rather than a performance or cost promise. Compare the actual silicon and software against the same requirements you would use for any embedded processor, and verify compatibility and support for the product’s intended lifetime.
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