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Hybrid bonding connects two semiconductor layers by bonding their dielectric surfaces together while simultaneously joining aligned copper pads. With no solder microbumps between the layers, the process can create very fine-pitch, short vertical connections for 3D chip integration. Its success depends on preparing exceptionally clean, flat surfaces and aligning the copper pads precisely.

How does hybrid bonding work?

A representative wafer-to-wafer process starts with two processed 300 mm wafers. Copper pads are formed in cavities in the bonding dielectric using a damascene-style process. Chemical mechanical polishing (CMP) then flattens the bonding surface while leaving the copper pads slightly recessed.

The wafers are aligned and brought into contact at room temperature. Initial adhesion between the dielectric surfaces creates a bonding wave that travels from the center toward the edge. A later anneal strengthens the interface, creating permanent dielectric-to-dielectric and copper-to-copper bonds.

The copper recess must be carefully controlled: the pads need to meet as the bond forms, while the surrounding dielectric surfaces also bond. Imec says its 2 μm die-to-wafer demonstration required minimal copper pad recess, below 2.5 nm, and careful CMP optimization of the Cu/SiCN surface. Imec’s May 29, 2024 release describes that requirement.

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What makes the interface difficult to form?

  • Cleanliness: Particles or contamination can interfere with the bond.
  • Planarity and topology: CMP must produce a sufficiently flat, controlled surface.
  • Copper recess: The copper pads must be recessed by the right amount relative to the dielectric.
  • Alignment: Corresponding copper pads must line up accurately.
  • Bond strength: The assembled interface must remain intact through the process.

Wafer-to-wafer versus die-to-wafer bonding

The main assembly distinction is whether the process joins whole wafers or places individual singulated dies onto a target wafer. Neither approach is universally superior; the application and assembly flow determine which is suitable.

Approach How it is assembled Key considerations Demonstrated example in the cited work
Wafer-to-wafer (W2W) Two processed wafers are aligned and bonded as whole wafers. Requires wafer-level surface preparation and alignment. Used in applications such as stacked image sensors; imec discusses extending the approach toward memory-on-logic stacking. Imec reported a 400 nm interconnect-pitch research demonstration in 2023. Imec and EV Group reported a 200 nm Cu interconnect pad-pitch test vehicle in 2026.
Die-to-wafer (D2W) Dies are singulated and placed individually onto a target wafer. Allows selected dies to be assembled, but singulation, clean handling, accurate placement, and throughput add challenges. Imec reported a 2 μm Cu bond-pad-pitch demonstration in 2024.

The assembly approaches and examples are described in imec’s overview of hybrid bonding, its 2024 D2W release, and its 2026 announcement with EV Group.

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What do the reported pitch figures mean?

Pitch is the spacing between repeated interconnects. A smaller pitch can fit more connections into a given area, but reported pitches should be read with their date, assembly type, and demonstration context in mind.

Reported pitch Assembly type and date What the source establishes
400 nm Wafer-to-wafer, 2023 Imec described Cu/SiCN bonding work presented at IEDM 2023, with design and process changes aimed at scaling interconnect pitch. Source
2 μm Die-to-wafer, 2024 Imec reported a demonstration with less than 350 nm die-to-wafer overlay error, Kelvin electrical yield above 85%, and daisy-chain electrical yield above 70%. These figures apply to that test vehicle and process flow. Source
200 nm Wafer-to-wafer, 2026 Imec and EV Group described a test vehicle with routable interconnects. This research demonstration is not a universal commercial production specification. Source

These figures are not directly interchangeable product specifications: they refer to different assembly types, demonstrations, and dates. The cited releases do not establish broad commercial deployment at each pitch.

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Why use hybrid bonding?

By enabling fine-pitch connections between stacked layers, hybrid bonding supports high-density 3D heterogeneous integration. Potential applications identified by imec include logic or memory stacked on logic, and memory stacked on memory. Wafer-level integration and the short vertical connections also make the approach relevant to advanced chip packaging.

These are applications the technology may enable, not evidence that every cited pitch is already used broadly in commercial products. The cited material focuses on specific research and test-vehicle demonstrations rather than a comprehensive account of manufacturers, production volumes, or deployment.

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