Brion’s Focus Exposure Modeling (FEM) added focus and exposure variation to full-chip lithography simulation, allowing engineers to evaluate optical proximity correction (OPC) across a process window rather than only at a nominal setting. Brion applied it in Tachyon OPC+ to help identify patterns and mask corrections that might fail before a photomask or wafer was made.
What Focus Exposure Modeling did
Optical proximity correction modifies mask patterns to compensate for the way a lithography system prints them. A correction that looks suitable at one set of manufacturing conditions may be less reliable if focus or exposure changes. FEM models those two variables so engineers can assess simulated printing behavior at multiple points in the intended process window.
Brion announced a beta FEM system in October 2005. The company described it as a way to simulate manufacturing conditions before photomask or wafer production and to find OPC and other reticle-enhancement problems earlier in the flow. EE Times’ 2005 report describes that launch and its stated purpose.
How Brion’s FEM model was calibrated and used
The model described in the 2006 SPIE paper had two adjustable parameters: focus and exposure. Calibration used wafer measurements from a limited number of sampling locations. Once calibrated, the model could generate simulations at other focus and exposure points, enabling analysis across the process window. The paper identifies lithography manufacturability checking (LMC) and OPC as applications. The paper’s abstract and description summarize those methods and uses.
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- Calibrate the model. Compare simulations with wafer measurements from sampled locations. A related patent describes varying focus and exposure while holding other fitting parameters constant, then comparing simulated and measured results and iteratively fitting the model. The patent describes that calibration approach.
- Simulate across the window. Generate results at selected focus and exposure combinations, including points beyond the measured sampling locations.
- Check manufacturability or refine OPC. Use the simulated results to identify patterns or corrections that may not remain printable across the intended conditions.
Why process-window-aware OPC mattered
As feature sizes shrank and the process factor k1 decreased, the available process latitude narrowed. A nominal-condition result alone does not show how a pattern behaves when focus or exposure moves away from its target. Evaluating those variations gives engineers a way to spot potentially fragile patterns earlier and choose corrections intended to remain printable across the planned window.
That is the practical distinction between a nominal-only check and FEM-based OPC: the latter brings focus and exposure variation into the simulated assessment. It does not, by itself, guarantee that every pattern will print successfully; the result depends on the model, calibration measurements, selected window and manufacturing process.
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What Tachyon OPC+ added
In February 2006, Brion introduced Tachyon OPC+, an OPC implementation built on its Tachyon hardware-accelerated, image-based data and simulation platform. Brion positioned OPC+ as applying focus-exposure modeling through the process window for full-chip OPC. The company also said processing speed scaled linearly with die size, making runtime per square millimeter predictable for large designs. That scaling description is Brion’s stated product claim in EE Times’ 2006 coverage, not an independently reported performance benchmark.
EDN likewise described Tachyon OPC+ as a hardware/software platform for sub-65 nm designs and through-process-window full-chip simulation. EDN’s product report provides that period-specific context; it should not be read as evidence of present-day product specifications or availability.
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Nominal-condition OPC and FEM-based OPC compared
The comparison below describes the conceptual difference relevant to Brion’s product. The cited historical reports do not establish a quantified, apples-to-apples comparison against a particular competing OPC system.
| Dimension | Nominal-condition OPC | FEM-based OPC as Brion described it |
|---|---|---|
| Focus and exposure coverage | Evaluates a nominal condition; coverage beyond it is not stated in the cited Brion reports. | Models focus and exposure across a defined process window. EE Times, 2006. |
| Calibration data | Not stated for a particular nominal-condition product in the cited sources. | The 2006 paper describes calibration from wafer measurements at limited sampling locations, followed by simulations at other focus and exposure points. SPIE paper. |
| Full-chip runtime | No comparative runtime or scaling figure is stated in the cited sources. | Brion said Tachyon OPC+ processing speed scaled linearly with die size, making runtime per square millimeter predictable; no independent benchmark is provided. EE Times, 2006. |
| Manufacturability coverage | A single nominal result does not, on its own, characterize behavior across focus and exposure variation. | Intended to assess printability through the modeled window and support LMC as well as OPC. SPIE paper. |
| Mask-tapeout integration | Specific integration details are not established by the cited sources. | Later ASML material describes Tachyon Flexible Mask Optimization (FMO), which supports multiple OPC techniques in one mask tapeout and applies intensive corrections where they are most beneficial. ASML’s 2012 release. |
Brion’s later product context—and what the history establishes
By 2012, ASML identified Brion as an ASML division and described Tachyon Flexible Mask Optimization, or FMO. FMO was presented as a way to combine multiple OPC techniques in a single mask tapeout, concentrating computationally intensive corrections where they would deliver the most benefit. This is related product context, not proof that FMO and Tachyon OPC+ were the same product or that either has a particular status today.
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- SEMICONDUCTOR EDUCATION USE: Suitable for classrooms, laboratories, engineering courses, STEM activities, and demonstrations of wafer structures and semiconductor manufacturing concepts.
- TECHNOLOGY DISPLAY ITEM: Ideal for exhibitions, science displays, collections, and demonstrations related to microelectronics and semiconductor technology.
- INDIVIDUAL PACKAGING: Each sample is separately packaged to help maintain surface cleanliness and reduce scratches during storage and handling.
The cited material documents product announcements and descriptions from 2005 to 2012. It does not establish whether Tachyon OPC+ or FMO is currently sold, supported, priced, or available in 2026, nor does it provide present-day performance benchmarks. The reliable takeaway is historical: Brion used FEM to make full-chip OPC evaluation sensitive to focus and exposure variation, with the aim of finding lithography and mask problems before production.
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