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AMD Vitis Model Composer connects MATLAB/Simulink designs to synthesizable IP for AMD FPGAs and adaptive SoCs. To use that IP in a larger Vivado design, choose an implementation flow and target, configure the hardware interfaces, generate and package the module, then add it to Vivado IP Integrator. You need valid Vitis Model Composer and Vivado licenses; check AMD’s current UG1483 guide for supported MATLAB versions, operating systems, Vivado license tiers and installation requirements before starting.

What Vitis Model Composer generates

Vitis Model Composer is a MATLAB/Simulink add-on for designing and simulating hardware-accelerated algorithms graphically. AMD describes it as providing optimized AI Engine, HLS and HDL blocks and generating synthesizable hardware IP for AMD adaptive SoCs and FPGAs, including Versal devices with AI Engines. It is not simply a way to export an arbitrary Simulink model unchanged: the design must use a supported hardware flow and meet that flow’s implementation and interface requirements.

In the HDL flow, Model Composer can generate an AXI4-Lite slave interface and export a Model Composer module to the AMD Vivado IP catalog. That packaged module can then be integrated into a larger design in Vivado. Generation is one stage of the FPGA process; synthesis, implementation and bitstream generation continue in the normal AMD tool flow. AMD documents these capabilities in its Vitis Model Composer product information and UG1483.

Choose the implementation flow

HDL, HLS and AI Engine blocks are different ways to implement hardware, not interchangeable labels for the same output. Select based on the target device, design goals and team experience; the exact supported options and constraints depend on the device and software setup.

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Approach What it means for the design Consider it when
HDL Use the HDL workflow to generate synthesizable HDL-based IP and configure its interfaces. The documented flow supports AXI4-Lite slave-interface generation and export of a module to the Vivado IP catalog. You need HDL-oriented implementation and packaged IP for integration in Vivado.
HLS Use HLS blocks as a hardware implementation option within Model Composer. The appropriate device support, interface setup and achievable timing or resource use depend on the specific design and tool configuration. Your team wants to build the design using the HLS-oriented flow and has checked its target-specific requirements.
AI Engine Use AI Engine blocks for supported AMD devices, including Versal devices with AI Engines. They can be combined with programmable-logic HDL or HLS blocks in a heterogeneous design. The target includes AI Engines and the architecture benefits from dividing work between AI Engine and programmable logic.

AMD’s product information and tutorials describe these block families and heterogeneous workflows, but they do not establish a universal timing, area or performance winner. Evaluate those outcomes for the specific device, algorithm, constraints and tool configuration rather than assuming one flow is always faster or smaller.

Generate and integrate the IP

  1. Build and simulate the algorithm. Create the Simulink model using the appropriate Vitis Model Composer HDL, HLS or AI Engine blocks. Simulation helps check model behavior, but by itself does not establish that the generated design meets hardware timing or works correctly on a board.
  2. Check the installation and supported environment. Consult AMD’s Vitis Model Composer User Guide, UG1483 2026.1, for supported MATLAB versions and operating systems, Vivado license tiers, installation requirements, code generation and IP-module interfaces. The reviewed guide is dated June 23, 2026; use the guide corresponding to the software release you intend to install.
  3. Select the target. Choose the supported device or board for the design, then configure the hardware subsystem and required interfaces. There is no single board that applies to every Model Composer design; selection depends on the target device and system requirements.
  4. Configure and generate the hardware output. Set the design’s interface requirements and generate the HDL or other flow output. For an HDL module intended for Vivado reuse, configure the supported AXI4-Lite slave interface if needed and export the Model Composer module to the Vivado IP catalog.
  5. Integrate in Vivado. Add the packaged module to Vivado IP Integrator and connect it into the larger design. Then continue through synthesis, implementation and bitstream generation in the normal AMD flow.
  6. Verify at the depth your project requires. Use simulation to check model behavior; where hardware confidence is needed, plan for hardware co-simulation or board-level verification as appropriate. AMD’s tutorials cover simulation, code generation, AXI interfaces and IP Integrator, including examples for heterogeneous Versal designs.

Choose the target board and verification strategy

Start with the actual AMD device or platform required by the product, then check UG1483 for target-device and board selection guidance. Do not select a board merely because it appears in a tutorial: the sources establish no universally required board. Verify that the chosen target supports the intended HDL, HLS or AI Engine implementation and that its interfaces fit the surrounding system.

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Simulation and hardware co-simulation serve different purposes. Simulation lets you examine modeled behavior without treating the result as proof of physical implementation. Hardware co-simulation adds a hardware-oriented verification step, but it should be chosen to answer a defined risk or validation need; it does not replace completing the Vivado implementation flow and verifying the finished system.

Similarly, a direct custom-code import and an optimized library block are not automatically equivalent choices. Use the relevant supported block or import route only after confirming that it matches the design’s target and interface needs. The evidence available here does not establish blanket performance or compatibility rankings for custom code versus library blocks.

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Licenses, pricing and version requirements

AMD states that a valid Vitis Model Composer and Vivado license is required. Its 2026 product listing gives two Vitis Model Composer add-on prices:

License option Part number AMD-listed price
Node-locked add-on EF-MATSIM-ADDON-NL $995, as listed by AMD in 2026; recheck current price and availability before purchase.
Floating add-on EF-MATSIM-ADDON-FL $1,995, as listed by AMD in 2026; recheck current price and availability before purchase.

Those are the add-on prices stated on AMD’s product page, not a complete estimate of every license or cost a project may require. Confirm the applicable Vivado license tier and the current purchase terms directly with AMD.

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UG1483 2026.1, dated June 23, 2026, is the current guide reviewed for this article. It covers MATLAB and operating-system support, Vivado license tiers, installation, target selection, code generation and IP-module interfaces. Since compatibility is release-specific, check that guide against the precise MATLAB, Model Composer and Vivado versions you plan to use rather than relying on a generic version claim.

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AMD documentation to consult

  • AMD’s Vitis Model Composer product information for product capabilities and license terms.
  • AMD’s Vitis Model Composer User Guide, UG1483 2026.1, for supported environments, installation, target selection, code generation and IP interfaces.
  • AMD’s Vitis Model Composer tutorials for simulation, code generation, AXI interfaces, IP Integrator and heterogeneous Versal examples.

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