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What EUV lithography and advanced packaging do
EUV lithography patterns tiny features onto silicon wafers during chip fabrication. Advanced packaging comes later: it brings separately fabricated dies and memory together in a package. These are complementary steps in a production chain, not competing ways to make the same part of a chip. A shortage or yield problem at either step can reduce the number of finished accelerators available to ship.
EUV patterns features on the wafer
ASML says its EUV systems use light with a 13.5 nm wavelength and play a critical role in high-volume manufacturing of leading-edge chips. Its EXE High-NA platform is described as using 0.55 numerical aperture optics and offering 8 nm resolution. ASML has said the platform would support high-volume manufacturing in 2025–2026; that is a company roadmap statement, not evidence that the platform has already increased AI-chip output.
Packaging combines dies and memory
TSMC describes CoWoS as an advanced 2.5D packaging technology that provides a foundation for high-performance computing and AI products. Packaging capacity and yield matter because a usable wafer die is not yet a completed package. The specific package design determines which integration process and production capacity are relevant.
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What company disclosures show
| Stage | Reported development | What it establishes—and what it does not |
|---|---|---|
| EUV equipment | ASML reported demonstrating a 1,000-watt EUV light source in April 2025. | This is a source-power milestone; it does not quantify scanner throughput in a fab or the supply of completed AI chips. |
| EUV equipment supply chain | ASML’s 2024 SEC filing identifies capacity at Carl Zeiss SMT, its sole supplier of specified critical optical components, as a limit on lithography-system production. | It identifies an upstream equipment constraint, not proof that EUV is the limiting step for a particular accelerator. |
| Wafer process yield | TSMC’s 2024 annual report says its lithography R&D included work to improve wafer yield for 2 nm risk production. | Scanner access alone does not determine usable die output; yield and process productivity also matter. |
| Advanced packaging | TSMC says CoWoS-R has been in volume production since 2023. Its 2025 annual report reports strong CoWoS growth due to surging AI demand since 2023. | These statements establish demand growth and production activity, but do not quantify a capacity shortfall, utilization, package yield or delayed accelerator shipments. |
| Package formats and capacity | TSMC reports CoWoS-L at 3.5-reticle size in production since 2024, with qualification of the 5.5-reticle size expected in 2026. It also says it expanded advanced-packaging capacity in Chiayi and Tainan during 2025. | The disclosures show technology development and expansion; they do not reveal how much usable capacity is available for any one chip design. |
The figures and dates above are company-reported statements, not independent measures comparing the two stages. TSMC also lists CoWoS, InFO and SoIC among the packaging and 3D-stacking technologies it is developing to meet customer needs.
Why investment or demand does not identify the bottleneck
Capacity investment is evidence that a company is responding to demand or preparing for future needs. It does not, by itself, show that the investment target is the step currently holding back shipments. Likewise, rising AI demand for CoWoS does not establish that packaging is tighter than wafer fabrication. Equipment availability, wafer yield, package capacity and the output of a particular chip design all affect the final result.
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A chip may also encounter constraints before a wafer reaches packaging. ASML’s reported optical-component constraint concerns production of lithography systems, while TSMC’s yield work concerns wafer manufacturing. Neither disclosure supplies a direct measure of how those issues affect a named accelerator’s deliveries. The relevant constraint can shift as suppliers add capacity, processes change or a product’s manufacturing mix changes.
What data would determine the limiting step
To compare EUV and packaging for a specific accelerator and delivery period, the evidence would need to line up across the same product and time window. At minimum, it would include:
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- Usable wafer starts on the process node used for the chip.
- EUV scanner availability and throughput, plus the number of critical layers patterned with EUV.
- Wafer yield and the number of usable dies produced per wafer.
- Capacity and yield for the advanced-package design used by that chip.
- Lead times, inventory and shipment volumes at both stages for the same period.
The cited company disclosures do not provide this matched dataset. Without it, a claim that one stage is categorically the current bottleneck goes beyond what these sources establish.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to read the next EUV milestone
In an announcement dated September 8, 2026, ASML and TSMC described a joint initiative involving larger-format EUV photomasks. TSMC said it intends to use ASML High-NA technology in high-volume manufacturing for advanced nodes starting in 2030. That is a future intention, not an achieved production capability or evidence about today’s accelerator output.
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