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An LLC resonant half-bridge is designed from a defined input/output and operating envelope—not from a universal set of component values. Its half-bridge drives a resonant tank with an approximately 50% duty-cycle square wave; the tank and transformer transfer energy, while the controller regulates output mainly by changing switching frequency. To make a high-power design reliable, calculate gain and stress across line and load, preserve primary-switch zero-voltage-switching (ZVS) margin, and validate the tank and control behavior before full-power testing.

What the converter does—and what “high power” does not specify

The primary half-bridge alternately applies a square-wave voltage to the LLC network. The network consists of resonant capacitance, resonant inductance, and the transformer’s magnetizing inductance. The transformer provides isolation and the turns ratio needed for the intended output; a secondary rectifier and output filter deliver DC. Transformer leakage, winding and layout parasitics, and the load reflected to the primary affect real behavior, so an idealized tank calculation is only a starting point.

Unlike a conventional PWM converter that primarily regulates by changing duty cycle, an LLC stage generally holds the half-bridge duty cycle near 50% and regulates by moving switching frequency relative to resonance. The required frequency range depends on the tank, turns ratio, input voltage, output voltage, load, and rectifier arrangement. There is no single “high-power” design point in the available examples: the title’s 400 V-class context does not establish a target power, output, cooling method, isolation specification, or compliance requirement.

For the underlying design framework, see STMicroelectronics’ LLC resonant half-bridge converter design guideline and Texas Instruments’ Power Tips: Designing an LLC Resonant Half-bridge Power Converter.

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Start with the operating envelope

Before selecting tank values or switches, write down the conditions the stage must meet. A nominal input/output point is not enough: the worst gain demand and semiconductor stress may occur at different corners of the operating range.

  • Minimum, nominal, and maximum DC input voltage, including expected bus variation.
  • Output voltage, continuous and peak current, rated power, and load range.
  • Startup, hold-up, load-step, and other transient requirements.
  • Isolation requirements, ambient temperature, cooling method, size limits, efficiency target, and protection behavior.
  • Rectifier and transformer arrangement, and whether synchronous rectification is appropriate.

Use these limits to determine the required conversion gain at minimum, nominal, and maximum input and load. Select a transformer turns ratio and rectifier topology that meet that gain envelope while keeping switch voltage/current stress and tank current manageable. Treat the bridge choice as a specification trade-off: half-bridge and full-bridge LLC are both options, but no matched numerical comparison establishes that one universally wins. Bus voltage, power, device stress, turns ratio, gain needs, and cost determine the choice.

Choose a tank and usable frequency range

Establish the nominal resonant point

Choose the intended nominal operating point, then calculate initial resonant capacitance, resonant inductance, and magnetizing inductance with a documented model such as the first-harmonic approximation (FHA). FHA simplifies the analysis by representing the switching waveforms with their fundamental components; it does not capture every switching transition or parasitic effect. Use it to make early calculations tractable, not as proof that the hardware will meet its targets.

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Check gain and soft-switching margin across corners

Plot tank gain against normalized switching frequency and load. Set the candidate minimum and maximum switching frequencies only after confirming that the full input/output envelope is reachable. Moving farther from resonance can extend the available gain range, but can also raise circulating current and lower efficiency. The frequency limits must also keep the stage in a suitable inductive operating region for primary ZVS.

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ZVS is not guaranteed by the LLC topology alone. The operating point, load, tank values, dead time, and commutation conditions all matter. Check margin at intended light-load states and during startup or transients, not just at nominal full load. If the required gain forces operation where commutation margin or current stress is unacceptable, revisit the turns ratio, tank design, operating envelope, or architecture rather than assuming a wider frequency sweep will solve the problem.

Design the magnetics, switches, and rectifier as one system

Transformer and resonant inductor

Design the transformer and resonant inductor for the required turns ratio and inductance targets while checking flux density, copper loss, core loss, insulation, temperature rise, and parasitic capacitance. Leakage and magnetizing inductance influence the tank, so characterize the built magnetic components rather than treating their nominal targets as exact. Include measured component and layout parasitics when refining the model.

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Primary half-bridge and gate drive

Rate primary MOSFETs and the gate drive for actual voltage and current stress, switching transitions, dead time, and thermal conditions. Account for startup and fault behavior as well as steady-state operation. A frequency range that works in a simplified gain plot may still produce excessive RMS or peak current, difficult switching transitions, or insufficient ZVS margin in hardware.

Secondary rectification and output filtering

Size rectifiers or synchronous switches and the output filter for secondary current and thermal stress. Synchronous rectification can reduce conduction loss where output voltage is low and current is high, but adds timing and control complexity and can introduce reverse-current or commutation concerns. Decide from the application’s operating points and validate the switching behavior.

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Gate-driver selection should likewise follow the design requirements: high-voltage rating, isolation needs, peak gate current, propagation delay, dead-time behavior, and switching-frequency suitability matter more than the “half-bridge” label alone. Related component categories include resonant controllers, power MOSFETs, transformer and magnetic materials, synchronous-rectification controllers, and measurement equipment; no particular device is specified by the design examples below.

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Build the frequency-control and protection behavior

The controller must regulate output over the calculated gain envelope while respecting the chosen frequency limits. Plan startup frequency behavior, loop stability, and transitions among operating states. If the application needs burst or other light-load behavior, include it in the control design and check its effects on regulation and soft switching. Define overcurrent, overvoltage, and overtemperature responses, plus safe shutdown and fault recovery.

Check loop stability and state transitions at minimum, nominal, and maximum input and across the load range. A controller that regulates at one point is not necessarily stable or well behaved near frequency limits, during load changes, or at startup. Ensure protection thresholds and timing are compatible with the power stage and its stored energy.

Validate progressively before full-power operation

Measure the resonant tank and transformer before testing at full operating conditions. Texas Instruments’ February 2024 guidance, Measure your LLC resonant tank before testing at full operating conditions, addresses this validation step. Compare measured tank behavior with the calculation, then refine the analysis using parasitic-aware simulation and switching-model validation.

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  1. Characterize components and the tank. Verify resonant and magnetizing parameters and account for transformer and layout parasitics.
  2. Test incrementally. Use isolated and differential measurement equipment appropriate to the high-voltage switching stage, and a load rated for the energy involved. Begin under controlled conditions and increase operating range deliberately.
  3. Check switching behavior. Observe switching transitions and commutation at relevant line and load points, including light load and transients, to establish ZVS margin.
  4. Map performance over the envelope. Record efficiency, component temperatures, regulation, and protection behavior across input voltage and load rather than reporting only a peak value.
  5. Revisit the design where measurements disagree. Update the model with measured component and layout parasitics, then repeat validation before claiming the operating envelope.
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What published examples do—and do not—show

The figures below belong to separate sources and should not be combined into a single converter specification.

Source and scope Published details How to interpret them
Electronic Design, “Designing a High-Power LLC Resonant Half-Bridge DC-DC Converter” 400 V-range DC input context and 200–350 kHz switching-frequency range; publication date not established on the retrieved page. Illustrative design context, not a universally optimal frequency range or a complete specification for a particular power stage.
Texas Instruments TIDM-RESLLC-DCDC reference design 300 W digitally controlled LLC half-bridge; 375–405 V DC input; 12 V, 25 A rated output; synchronous rectification. TI reports more than 90% efficiency across a wide load range and peak efficiency above 93%. Page accessed 2026; no publication year is shown in the retrieved page. A specific 300 W reference implementation, not measured performance evidence for a higher-power design. TI describes it as developed for testing and performance validation; the assembled board is not available for sale. The page provides design guides, BOM, PCB layout, and schematics.

TI describes TIDM-RESLLC-DCDC as “a digitally controlled 300W resonant LLC half-bridge DC/DC converter with added synchronous rectification.” Use its design files as a worked reference, not as a substitute for re-deriving stresses, thermal limits, and control behavior for a different specification.

When to consider multiple stages

For a higher power target, compare a larger single stage with multiple interleaved stages using the same input/output envelope. Compare gain range, frequency extremes, ZVS/ZCS margin, tank RMS and peak current, semiconductor stress, transformer size and losses, efficiency across line and load, thermal rise, EMI, control complexity, startup and fault behavior, isolation, and measured cost and size. If stages are paralleled, provide explicit current sharing and coordinated control and protection; the examples above do not establish validated high-power scaling performance.

Design decision in brief

A sound LLC half-bridge design is the result of matching the input/output envelope to the turns ratio, tank, frequency range, switches, magnetics, rectification, and control—then checking the complete operating envelope in simulation and hardware. Treat published frequency and efficiency figures as properties of their stated contexts, not as design targets that transfer automatically to another converter.

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