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A 400G composable SmartNIC is not just a fast Ethernet interface: it is a packet-processing pipeline implemented in reconfigurable FPGA logic, plus the buffering, PCIe DMA, driver, host software, and server infrastructure needed to make that pipeline usable. This guide explains the architecture proposed in Achronix personnel’s April 26, 2024, Electronic Design article and turns it into an integration plan. It is an architecture guide—not an independently tested build, a released bitstream, or a verified recipe for a particular card.
What “composable” means in this design
The article uses “composable” to describe dynamically reconfigurable logic connected by an on-chip mesh, rather than CPU instructions running on cores connected through fixed data buses. In practical terms, the integrator assembles packet-processing stages in FPGA logic and connects them into a datapath suited to a workload. This is a specific use of the term; it does not mean every SmartNIC or DPU can be reconfigured in the same way.
The article presents a soft, multi-stage pipeline. Its stages receive and buffer packets, extract fields and metadata, identify existing flows, apply rules to new flows, run workload-specific logic, and transfer data to host memory. The architecture is a useful mental model, but the article does not provide a reproducible implementation, independent benchmark, or released bitstream. It also described a proposed Generic Flow Table stage as under development when published; that statement is not confirmation of its current release status.
How a packet moves through the pipeline
- Ethernet interface and buffering. The packet interface receives traffic and conditions it for downstream processing. The described design buffers packets in a FIFO in external memory so later stages can consume them when ready. The article’s 400GbE example uses a four-NAP design; those are details of that example, not requirements for every 400G FPGA SmartNIC.
- Parser and metadata. A receive-side parser separates packet headers, performs basic transformations, and attaches metadata used by later stages. The proposed parser can unwrap virtualization protocols and pass packet data to customer or integrator logic.
- Known-flow lookup. Parsed header fields are used to derive a hash for flow lookup. On a hit, the design records statistics and applies the action associated with the existing flow.
- Rules for a new flow. On a miss, a rules engine selects the first-packet action and creates a flow entry. The article describes configurable uses including access control, DDoS defenses, string searches, and deeper packet inspection. These are described capabilities, not independently validated performance or security results.
- Custom processing and DMA. Workload-specific logic processes the packet as required, after which a PCIe-facing DMA stage transfers data to host buffers. The exact processing and transfer behavior must be designed around the FPGA, card, and application.
Step-by-step integration plan
1. Specify the workload and packet path
Write down which ports and directions carry traffic, which protocols and encapsulations must be recognized, what actions must happen before packets reach the host, and what can remain in software. Identify the target traffic mix and latency, throughput, and packet-loss goals. The Achronix article frames FPGA logic as customizable for use cases such as access control, security processing, and storage; it does not establish that one pipeline configuration suits all of them.
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2. Select a card and map its resources
Confirm that the exact board supports the required Ethernet mode and transceivers, and that its FPGA logic, memory, development flow, board form factor, PCIe connectivity, and cooling fit the design. A documented commercial example is Napatech’s N3070X, which lists an Agilex FPGA, two QSFP-DD ports configurable as 1×400GbE, 2×200GbE, or 4×100GbE, three PCIe Gen5 x16 interfaces, DDR4 configurations, optional CXL 2.0 mount options on host and expansion interfaces, and secure boot/configuration options. These are N3070X product specifications, not evidence that it implements the Achronix article’s pipeline.
3. Verify Ethernet, optics, and buffering
Check the actual MAC/PCS configuration, link standard, switch compatibility, module qualification, fiber type, and optical reach. Select a QSFP-DD 400G Ethernet optical transceiver only after confirming compatibility with the specific card and the other end of the link. Set FIFO capacity and define what happens when downstream stages cannot keep up: backpressure, buffering limits, and packet drops are system behaviors that must be made explicit. Do not assume the article’s FIFO or four-NAP arrangement maps directly to a different board.
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4. Define parser fields and metadata
List the headers and tunnel formats the parser must understand, including any virtualization-protocol unwrap requirements. Specify which parsed fields form the flow key and what metadata each downstream stage needs. Bound the parser’s work to the workload and map it against the FPGA’s available logic and memory; support for an example protocol in an architecture description is not proof that a particular card or design already implements it.
5. Design flow state and first-packet policy
Separate the established-flow fast path from the rule evaluation needed for a new flow. Before implementation, decide how entries are populated and aged, how concurrent updates are handled, who owns control-plane changes, and how counters are read or cleared. The article mentions flow preload and statistics tooling, but does not specify a complete lifecycle implementation for these details. Its proposed Generic Flow Table was under development when the article appeared, so confirm availability and interface details with the relevant vendor rather than assuming that proposed stage is ready to use.
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6. Add only the required custom logic
Choose the packet actions that belong in programmable logic and estimate their resource and memory costs. The article gives examples such as checking DDoS-related header or payload conditions, searching for predefined keywords, and performing destination-specific inspection. Treat these as examples of possible processing, not as proof of security efficacy, throughput, or suitability for a particular traffic pattern.
7. Choose and test a DMA strategy
The article contrasts two DMA approaches. Its qualitative guidance is that ring mode uses PCIe efficiently but requires a host memory copy, while scatter/gather avoids that copy but may generate small, fragmented reads and writes that use PCIe less efficiently. It says small-packet performance usually favors ring mode and larger average packet sizes favor scatter/gather. There is no published crossover point in the article: measure both approaches with the target packet-size distribution, batching, host application, memory-copy budget, and PCIe transaction pattern before choosing.
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8. Build the host software and operations path
A datapath needs software that can configure and operate it. The article says the design’s software path calls for a PCIe device driver connecting the DMA engine to user-space host buffers, plus SDK tools for transceivers, flow and rules loading, statistics, and samples. That is the article’s description of the intended SDK composition, not confirmation that those tools are currently released. Verify present driver, SDK, operating-system, and support status with the vendor before committing to a platform.
9. Qualify the card in the target server
Check the server’s PCIe generation, lane width, slot wiring and topology, auxiliary power, chassis clearance, module power, airflow, and operating temperature. Board limits are not interchangeable: the N3070X specifies up to 150W platform power dissipation with passive cooling. Separately, N3076X installation documentation states up to 150W including two modules and requires 5.5m/s airflow for operation up to 45°C at its maximum supported power. Those N3076X conditions must not be applied to the N3070X or another card.
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10. Establish a workload-specific validation plan
Before claiming line-rate behavior, measure the actual system under representative conditions. Record packet sizes and directions, throughput, packet loss, latency distribution, host CPU use, DMA mode, flow-table hit and miss rates, and thermal state. The Achronix architecture article supplies no independent reproducible benchmark, bitstream, or test methodology, so its design description alone cannot substantiate a performance claim.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What to compare before choosing an architecture
A composable FPGA SmartNIC, a DPU, and another programmable SmartNIC may all target 400G-class systems, but their feature lists do not establish a universal winner. Compare them against the same workload and deployment constraints.
| Reference | What the cited material describes | How to interpret it |
|---|---|---|
| Achronix/Electronic Design architecture article (2024) | FPGA pipeline with packet interface and buffering, parsing, flow lookup, rules, custom logic, and PCIe DMA. | Vendor-authored architecture guidance; not an independent build report or verified performance result. |
| Napatech N3070X | Agilex FPGA; two QSFP-DD ports supporting 1×400GbE, 2×200GbE, or 4×100GbE; three PCIe Gen5 x16 interfaces; DDR4 configurations; optional CXL 2.0 mount options; up to 150W platform dissipation with passive cooling. | A product-specific platform example. Validate current specifications and server compatibility; it is not proof of equivalence to the article’s design. |
| NVIDIA BlueField-3 | The hardware manual describes Arm cores, an RDMA adapter supporting up to 400Gb/s, PCIe Gen5, RoCE, storage acceleration, SR-IOV, GPU Direct, and cryptographic/security functions. | A DPU-oriented alternative with a distinct architecture. Compare programmable stages, fixed-function offloads, ecosystem, host/fabric integration, isolation, power, and workload fit; the cited sources contain no controlled direct performance or cost comparison. |
| AMD 400G Adaptive SmartNIC SoC presentation (2022) | AMD’s Hot Chips 34 presentation reports “400Mpps Ingress + 400Mpps Egress” for programmable-logic packet rate and “400Gbps RX + 400Gbps TX” for full Virtio.NET offload bandwidth. | Vendor presentation figures for AMD’s separate architecture—not measurements of the Achronix design or a controlled comparison. |
These references describe different products or architectures. Choose by which processing stages must be customized, which fixed-function offloads are useful, how the software ecosystem fits the host and fabric, and what power, cooling, and operational requirements the deployment can support.
Quick Recap
Deployment checklist
- Document traffic direction, protocol and tunnel requirements, target packet mix, and which actions run in hardware versus on the host.
- Confirm the exact card’s Ethernet modes, qualified modules, FPGA resources, memory, PCIe topology, power, cooling, and supported development and software stack.
- Define parser fields, metadata, flow keys, first-packet rules, state ownership, update behavior, and statistics needs.
- Budget FIFO capacity and decide how the datapath handles backpressure and overload.
- Measure ring and scatter/gather DMA against the intended workload instead of relying on a universal packet-size threshold.
- Test throughput, loss, latency, CPU use, flow hit/miss behavior, and thermal state in the target server before making performance claims.
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