Behavior-based design debugging analyzes what an RTL or gate-level design actually does over time, then connects that behavior to the logic and inputs that caused it. The original Verdi approach, described in a 2002 article, aimed to reduce the manual work of correlating source code, design structure, and simulation waveforms. Today, Synopsys Verdi has expanded into a debug and verification-management platform with waveform, source, protocol, regression, and other analysis capabilities.
What behavior-based debugging means
A waveform shows signal values over time, but a signal trace alone does not necessarily explain why a failure occurred. Engineers often have to connect the trace to RTL statements, logic structure, control conditions, and earlier events. That mental reconstruction becomes harder in large designs or unfamiliar blocks.
Behavior-based debugging tries to make those connections explicit. The tool analyzes design descriptions and simulation results to construct an internal model of the design’s behavior over time. Engineers can then inspect active control and data paths, trace signals backward, and move between observed behavior and the logic that produced it.
In the 2002 account of Novas Software’s Verdi, the aim was to automate the time-consuming process of revealing IC behavior—not merely to search design structure or display waveforms. Novas president and CEO Scott Sandler said at the time: “The difficulty of understanding how designs work and why they don’t continues to increase exponentially, particularly for SoCs, where both chips and the teams that design them are large and complex, and much of the design is unfamiliar to the design and verification engineers.”
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How the original Verdi workflow worked
Build a model from design descriptions and simulation
Verdi’s behavior analysis inferred logic functions from RTL or gate-level descriptions and interpreted simulation results. It used these inputs to build an internal representation of actual design behavior over time, giving the engineer a basis for investigating a failure rather than starting from disconnected signal values.
Visualize active logic paths
Register-flow and statement-flow graphs presented control and data flow. By showing which logic paths were active, these views helped narrow the investigation to the parts of the design involved in a particular event. Engineers could also trace a signal backward through time to examine the conditions and earlier activity that led to its current value.
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Explore local what-if changes
Symbolic Design Exploration supported local analysis without requiring every question to begin with a full edit-and-resimulation cycle. Its “evaluate” operation propagated modified values forward; “justify” searched backward for inputs that could explain a requested value. These operations were intended to help engineers test hypotheses and understand cause-and-effect relationships in the design.
How this differs from manual waveform tracing
Manual waveform investigation remains useful: engineers inspect signal transitions, find when expected and actual behavior diverge, and correlate that point with source or logic. The limitation is the amount of context an engineer must assemble by hand. A behavior-oriented flow adds analysis and linked views that can expose relevant paths and earlier causes.
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| Investigation approach | What it provides | Where the work remains |
|---|---|---|
| Waveform-led manual tracing | Signal values and transitions over time | The engineer correlates traces with statements, structure, control conditions, and prior events. |
| Behavior-based analysis | An inferred view of design behavior, active paths, and backward signal tracing | The engineer still interprets the evidence, chooses hypotheses, and determines whether the behavior is a design bug, testbench issue, or specification mismatch. |
Behavior-based analysis can reduce navigation and correlation effort; it does not replace engineering judgment or guarantee that every failure’s root cause is identified automatically.
What Synopsys Verdi does today
Synopsys describes Verdi as a debug and verification-management platform, a broader role than the behavior visualization emphasis in the 2002 article. Its documented capabilities include waveform viewing and comparison, source browsing, schematic and state-machine views, protocol analysis, low-power and assertion analysis, AI-based advanced debug, regression automation, and coverage-related workflows. Synopsys also describes an FSDB signal-database ecosystem.
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Optional hardware/software synchronized debug combines instruction-accurate processor visibility with RTL, C, and assembly views. The broader platform context connects verification planning, test execution, and coverage aggregation with simulation, emulation, and prototyping solutions. These functions place current Verdi in the surrounding verification lifecycle as well as interactive waveform and source investigation.
For current features and product scope, see Synopsys Verdi and the Synopsys verification-management overview.
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How to evaluate a debug workflow
When comparing Verdi with another debug setup, or deciding whether behavior-oriented analysis is useful for a project, assess the workflow across these dimensions:
- Behavior and root-cause analysis: Does it infer behavior and trace causes across time, or primarily display signal values?
- Cross-probing and explanation: Can engineers move between waveforms, RTL, source, schematics, statements, state machines, and protocols while retaining context?
- Automation: Does it support symbolic what-if exploration, regression triage, AI-assisted analysis, waveform reuse, or coverage-driven workflows?
- Flow integration: Does it connect to the project’s simulators, emulators, FPGA or prototyping systems, verification-management data, and hardware/software debug needs?
The right balance depends on the failure being investigated and the design flow. A team focused on a single simulation trace may value fast waveform navigation; a large SoC program may benefit more from cross-view analysis, regression support, and synchronization across software and hardware contexts.
Historical claims and availability are not current specifications
The June 2002 article described Verdi as bundled with Debussy technology, with Unix and Linux shipment planned for July 2002 and initial Verilog support; VHDL and mixed-language support were described as planned. Those statements are historical and should not be used to infer current platform support or packaging. The same article reported a “2x performance” improvement to Debussy’s Design Knowledge Architecture; that was a product claim, not an independently validated benchmark.
Sandler also characterized behavior-based debug as “the technology revolution needed to minimize debug time and avoid stretching schedules in the face of unrelenting design challenges.” That is a historical executive statement, not a measured guarantee of schedule or productivity improvement.
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