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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsArm’s Ethos-U65 extended its microNPU family beyond microcontrollers: it can be integrated into Cortex-A, Cortex-R and Neoverse-based systems, including application processors with DRAM and richer operating systems. The change lets an application-processor system use a dedicated, efficient accelerator for local machine-learning inference; it does not mean Arm sells a consumer processor called “microNPU.”
What Arm’s microNPU is
A microNPU is a compact neural processing unit (NPU) IP block for running machine-learning inference efficiently on a device. Arm introduced the Ethos-U55 in February 2020 for low-power embedded and IoT designs, pairing it with the Cortex-M55 microcontroller. Arm described that combination as delivering a 480× uplift in ML performance for microcontrollers; this is Arm’s 2020 claim, not an independently reproduced benchmark. Arm’s Ethos-U55 and Cortex-M55 announcement
Arm develops and licenses processor IP rather than selling Ethos-U chips directly. A chip designer integrates an Ethos-U NPU into a system-on-chip (SoC), alongside a host CPU and memory system. The resulting product’s actual capabilities depend on that integration, its software and the workloads it targets.
How Ethos-U moved from Cortex-M to application processors
When Arm announced Ethos-U65 in October 2020, it expanded the family to Cortex-A, Cortex-R and Neoverse-based systems. These can have richer operating systems and DRAM-backed memory than the small SRAM-and-flash environments common in microcontroller designs. Arm said the U65 delivered twice the on-device ML performance of the U55 while extending the microNPU approach to these systems. Arm’s October 19, 2020 Ethos-U65 announcement
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The architectural shift is about where a compact inference accelerator can be integrated: it can sit alongside an application-class CPU in a system designed for Linux or another rich OS, rather than being limited to a microcontroller-oriented design. Arm describes a common development flow across Cortex and Ethos-U processors. Its product documentation also describes Arm NN and Arm Compute Library as a software stack for translating neural-network frameworks to Cortex CPUs, Mali GPUs and Ethos NPUs. Software and operator support in a shipping product still depend on the SoC vendor’s implementation.
Ethos-U55 and Ethos-U65 compared
| Aspect | Ethos-U55 | Ethos-U65 |
|---|---|---|
| Typical system role | Microcontroller-class designs, paired in Arm’s original announcement with Cortex-M55. | Application-processor and other richer systems, including Cortex-A, Cortex-R and Neoverse designs, according to Arm. |
| Arm-published throughput and area | Up to 0.5 TOP/s and 90% energy reduction in about 0.1 mm², per current Arm product documentation. These are Arm specifications, not independent test results. | 1.0 TOP/s in about 0.6 mm² at 16 nm, per current Arm product documentation. The area and throughput describe Arm’s cited configuration. |
| Memory and software context | Suited to the smaller SRAM/flash constraints typical of deeply embedded systems; exact memory and software support depend on the implementation. | Designed to support richer environments, including DRAM-backed systems; exact support depends on the SoC and its software. |
| Workloads | Embedded inference; workload suitability depends on model, latency and implementation. | Arm cites vision and voice workloads; suitability depends on model, latency and implementation. |
TOP/s indicates peak operations per second, but it does not by itself predict energy per inference or sustained system power. Arm’s figures are configuration- and workload-dependent specifications. When evaluating a device, check memory bandwidth, supported operators, model size, latency and energy under the intended workload rather than comparing peak throughput alone.
Which application processors include Ethos-U65?
NXP’s i.MX 93 is a concrete application-processor example: NXP identifies the family as combining Arm Cortex-A55 cores with an integrated Ethos-U65 microNPU. NXP positions it for Linux-based edge applications needing machine learning with attention to cost and energy efficiency. NXP i.MX 93 application processor
This example shows how Arm’s licensed IP appears in a named SoC family. It does not establish that every i.MX 93 configuration, software image or workload has identical performance; check NXP’s product and software documentation for the specific device and deployment.
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Can an edge device run vision and voice inference locally?
Yes, a device built around a suitable Ethos-U65 implementation can be designed to run supported vision or voice inference on the device, without sending every inference to a remote service. Arm explicitly cites both workload categories for the U65. Whether a particular application runs well depends on the model and its operators, available memory and bandwidth, latency target, software support and sustained power budget.
- For vision: verify the model’s input size, operator coverage, frame-rate target and memory requirements.
- For voice: check the model’s supported operators, audio-processing pipeline and latency target.
- For either workload: confirm the SoC vendor provides compatible drivers and an optimized software path, then assess energy per inference and sustained system power.
Local inference can reduce reliance on a network connection and keep processing on the device, but those benefits do not guarantee a particular level of privacy, responsiveness or energy savings. Those outcomes depend on the product’s full design and software.
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- LuckFox Pico is a mini Linux development board based on the RV1103 chip, designed to provide developers with a simple and efficient development platform; Supports multiple interfaces, including MIPI CSI, GPIO, UART, SPI, I2C, USB, etc., for quick development and debugging
- Processor: Cortex A7@1.2GHz + RISC-V; Neural Network Processor (NPU): 0.5 TOPS, supports int4, int8, int16; Image Processor (ISP): Input 4M @ 30fps (Max)
- Memory: 64MB DDR2; USB: USB 2.0 Host/Device; Camera interface: MIPI CSI 2-lane; GPIO: 25 GPIO pins; Network port: 10/100M Ethernet controller and embedded PHY; Default storage medium: SPI NAND FL ASH (128MB)
- Built in Micro's self-developed 4th generation NPU, with high computational accuracy and support for mixed quantization of int4, in8, and int16. Among them, int8 has a computing power of 0.5 TOPS and int4 has a computing power of up to 1.0 TOPS
- Built in self-developed 3rd generation ISP3.2, supports 4 million pixels, and supports various image enhancement and correction algorithms such as HDR, WDR, and multi-level denoising
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