Android on RISC-V is real platform work, but it is not yet evidence of a finished, widely available Android phone. Google’s AOSP project reported a RISC-V virtual device reaching the home screen in 2025; Android 16’s compatibility definition later listed riscv64 as a native ABI; and BayLibre reported initial Android 16 functionality on a RISC-V development board in May 2026. Device compatibility, performance tuning and consumer availability are separate milestones.
Can Android run on a RISC-V processor?
Yes, in development environments and on at least one reported physical development-board setup. The strongest evidence is at different levels: a virtual-device target in AOSP, a later Android compatibility-specification entry for the riscv64 ABI, and BayLibre’s report of initial Android 16 functionality on a SpacemiT K1-based board. None of those alone means that a finished Android phone is ready to buy.
AOSP’s virtual-device target
Google’s android-riscv64 project repository documents the aosp_cf_riscv64_phone Cuttlefish target. Its status note for 2025 Q2 says the virtual device could run ART, Android’s runtime, and boot to the home screen, with shell and command-line tools working. That is meaningful operating-system progress, but it describes a virtual device rather than a retail handset.
A physical development-board bring-up
On May 13, 2026, BayLibre reported initial Android 16 functionality on a SpacemiT K1 system-on-chip, identified as RISC-V RVA22 with RVV 1.0, with tests performed on the BananaPi F3 K1 platform. BayLibre reported a boot time of less than two minutes on that platform, while explicitly noting that performance-optimization tuning had not yet been done. This is the company’s project-reported result, not an independent benchmark or a guarantee that another RISC-V board will behave the same way. See BayLibre’s Android 16 on RISC-V announcement.
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What the Android 16 riscv64 ABI listing means
The Android 16 Compatibility Definition, updated December 2, 2025, includes riscv64 in its native ABI list. An ABI, or application binary interface, defines how compiled native code interacts with an operating system and hardware. This matters for formal platform work: Android’s compatibility documentation recognizes riscv64 as an ABI relevant to compatible implementations.
It is not a certification announcement for a particular RISC-V device. The Compatibility Definition sets requirements for compatible implementations, and the document requires applicable implementations to meet the full requirements, including the Compatibility Test Suite (CTS). An ABI entry does not establish that every Android app or native library is available for RISC-V, or that any named board has passed compatibility testing. Read the Android 16 Compatibility Definition for the specification itself.
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- CH32V003 Development Minimum System Board for Nano RISC-V CH32V003F4U6 Chip TYPE-C USB 22Pin
- on-board 24MHz Crystal oscillator
- Power by TYPE-C USB
Dates matter when reading the status. AOSP’s 2025 Q2 repository note said the RISC-V NDK ABI was not yet defined at that time, described support as provisional, and warned that ABI changes were possible. The later Android 16 compatibility document includes riscv64 in its ABI list. These statements describe different sources and dates; the later listing is important progress, but it does not by itself establish a complete commercial device.
What remains between a board demo and a usable Android device?
Getting Android components to boot is only one part of device readiness. A product also needs working hardware support, the right interfaces between Android and vendor components, validated compatibility, adequate performance, and a path to distribution and support.
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- The ESP32-C3 SUPERMINI is positioned as a high-performance, low-power, cost-effective IoT mini development board, suitable for low-power IoT applications and wireless wearable applications
- It is equipped with a rich set of interfaces, including 11 digital I/Os that can be used as PWM pins and 4 analog I/Os that can be used as ADC pins.
- It supports four serial interfaces, including UART, I2C, and SPI.
- The ESP32-C3 features a 32-bit RISC-V CPU, including an FPU (Floating Point Unit) capable of 32-bit single-precision
- Package: 2PCS ESP32-C3 MINI Development Board ESP32 SuperMini ESP32 C3 WiFi Module
Kernel, graphics and hardware interfaces
BayLibre described porting vendor-kernel 6.6 drivers to Android kernel 6.19, adding Android support to the Imagination Vulkan implementation in Mesa, using generic HAL components for thermal management, USB and audio, and integrating a SpacemiT device configuration into the Android 16 build. These are examples of the device-specific integration work behind the reported board bring-up; they are not evidence that every peripheral or graphics feature is production-ready.
Compatibility testing and device completion
A 2026 FOSDEM session description on Open Source RISC-V AOSP porting discusses remaining work around graphics, HAL and vendor interfaces, Generic System Image (GSI) support, SELinux, partition layout, boot flow, and AOSP gaps. It frames full device bring-up and CTS/VTS compliance as milestones, not completed achievements. CTS is the Compatibility Test Suite; VTS is the Vendor Test Suite, which tests vendor implementations against Android requirements.
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- ESP32-C6 WiFi 6 microcontroller development board adopts ESP32-C6-WROOM-1-N8 module, which is equipped with RISC-V 32-bit single-core processor, up to 160MHz main frequency, built-in 8MB Flash
- Integrates WiFi 6, Bluetooth 5 and and IEEE 802.15.4 (Zigbee 3.0 and Thread) wireless communication, with superior RF performance
- Integrates rich peripherals including SPI, UART, I2C, I2S, LED PWM, SDIO and other interfaces, compatible with the pinout of ESP32-C6-DevKitC-1-N8 development board, more convenient to use and expand a variety of peripheral modules
- Onboard CH343 and CH334 USB HUB chips, supports USB and UART development at the same time via a USB-C port
- Comes with online examples and tutorials for ESP-IDF development environment
How ready is Android on RISC-V?
| Readiness level | What the evidence establishes | What it does not establish |
|---|---|---|
| AOSP virtual device | Google’s 2025 Q2 status note reports a Cuttlefish RISC-V target reaching ART and the home screen, with shell and command-line tools working. | A working retail phone or complete physical-device support. |
| Physical development board | BayLibre reports initial Android 16 functionality on the BananaPi F3 K1 platform with a SpacemiT K1 SoC. | General support for all RISC-V boards, finished performance tuning, or CTS/VTS completion. |
| Compatible consumer device | The Android 16 compatibility definition includes riscv64 in its ABI list, while compatibility requires meeting the applicable requirements. | A named, certified, widely available Android phone based on RISC-V. |
The key distinction is between architecture support, a particular hardware implementation, complete device integration, app and native-code availability, and an actual product launch. Progress at one level does not automatically complete the next.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Can you install Android on a RISC-V board?
The available report establishes that BayLibre ran its Android 16 work on the BananaPi F3 K1 platform, but it does not establish a standard public image that any owner can install or a guaranteed reproduction procedure. Treat the board as development hardware associated with an engineering bring-up, not as a ready-made Android phone. The project announcement identifies the platform and engineering work; check the project’s own published build instructions and support status before attempting an installation.
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- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
Google’s 2023 overview, Android and RISC-V: What you need to know to be ready, provides background on why Android began accepting RISC-V work, but it predates the later milestones above and should not be read as a current device-readiness report. The older RISC-V Android community repository is marked as archived, with current work directed upstream.
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