AMD’s EPYC 7002 “Rome” processors changed the server-platform equation at their August 7, 2019 launch: the family scaled to 64 Zen 2 cores per socket and paired that density with eight DDR4 memory channels and 128 PCIe 4.0 lanes. Those were family maximums, not features present in every model or server configuration. The practical gains depended on workload, memory population, system design, software, and price—and did not eliminate every single-thread or compatibility trade-off.
What EPYC 7002 changed at launch
AMD announced EPYC 7002 on August 7, 2019, as its second-generation EPYC family. Its central proposition was more than a higher core count: a server could combine many cores in one socket with substantial memory bandwidth and a large pool of high-speed I/O lanes. That combination could reduce the number of processors or systems needed for work that scales across cores, while giving storage and networking devices more expansion capacity.
AMD president and CEO Dr. Lisa Su described the launch as setting “a new standard for the modern datacenter” and delivering “record-setting performance and significantly lower total cost of ownership across a broad set of workloads.” Those are launch-era vendor claims, not a timeless performance verdict. The AMD launch announcement tied its results to particular benchmarks and test conditions.
Family platform capabilities
AMD’s EPYC 7002 family page describes configurations supporting up to 64 cores and 128 threads, up to 4 TB of DDR4 memory across eight channels, and 128 PCIe 4.0 lanes. These are ceilings for the family and platform, not a guarantee that every SKU, motherboard, or populated system reaches every maximum. Theoretical bandwidth, capacity, and lane count also do not directly predict application performance.
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What the launch numbers do—and do not—show
AMD said the family set 80 performance world records and delivered up to twice the performance of the previous generation. It estimated 25% to 50% lower total cost of ownership against competitive offerings. AMD also claimed up to 23% more instructions per clock per core on server workloads versus the prior generation; its footnote limits that comparison to internal testing on selected workloads at ISO frequency. These figures describe AMD’s 2019 claims, not independently established results for every buyer’s application.
AMD cited workload-specific gains as well, including up to 83% better Java application performance and up to 43% better SAP SD 2 Tier performance than competitors, plus up to twice the computational-fluid-dynamics performance. Such figures apply to the benchmark configurations and conditions behind the launch release; they should not be read as universal application gains.
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For memory, AMD specified eight DDR4-3200 channels with 204.8 GB/s theoretical bandwidth. Its launch comparison put this against 140.8 GB/s for a specified class of second-generation Intel Xeon Scalable processors. Both the comparison and the resulting bandwidth figures need their platform context: theoretical bandwidth is not measured application throughput, and actual performance depends on system configuration and workload.
EPYC 7742 and other model-level differences
The 2020 AMD datasheet is the appropriate reference for distinguishing individual SKUs. The EPYC 7742 illustrates the high-core-count model: 64 cores and 128 threads, 2.25 GHz base frequency, up to 3.40 GHz boost, 225 W TDP, 256 MB L3 cache, eight DDR4-3200 memory channels, 204.8 GB/s theoretical bandwidth, 128 PCIe Gen 4 lanes, and support for one- or two-socket configurations. The figures are specifications, not a promise of sustained clock speed or application performance.
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| Model | Cores / threads | TDP | Cache | Socket support |
|---|---|---|---|---|
| EPYC 7742 | 64 / 128 | 225 W | 256 MB L3 | 1P / 2P |
| EPYC 7702 | 64 / 128 | 200 W | 256 MB L3 | 1P / 2P |
| EPYC 7702P | 64 / 128 | not stated (AMD datasheet) | not stated (AMD datasheet) | 1P only |
| EPYC 7232P | 8 / 16 | 120 W | 32 MB L3 | 1P only |
“P” models are single-socket-only parts; do not plan a dual-socket build around one. For full SKU specifications and footnotes, consult AMD’s EPYC 7002 series datasheet (April 2020).
Why workload and full-system comparison matter
A high aggregate core count is most useful when the application can keep those cores busy. Database latency, lightly threaded services, virtualization density, high-performance computing, and I/O-bound jobs can respond differently to the same processor. A sound comparison uses the intended workload and keeps the rest of the system—and the benchmark method—visible.
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- Workload and benchmark: Compare the application or representative benchmark that matters, including throughput and latency where relevant.
- Socket and core count: Separate single-socket from dual-socket systems and account for software licensing that scales with cores or sockets.
- Memory: Record DIMM capacity, speed, channel population, and NUMA placement. A theoretical bandwidth maximum is not a substitute for a populated-system result.
- I/O topology: Verify usable PCIe lanes and how the system allocates them among storage, accelerators, and network adapters.
- Power and cooling: Compare processor TDP alongside complete-system energy under the workload. Boost behavior depends on platform limits and cooling.
- Total cost: Include system acquisition, software licenses, electricity, cooling, and operations. AMD’s launch TCO estimate is not a substitute for calculating costs for a particular deployment.
- Test conditions: Preserve benchmark version, compiler and software setup, system configuration, and test date; distinguish vendor-submitted or internal results from independent tests.
Single-thread performance and evidence quality
Rome’s throughput story did not mean it won every performance category. Ars Technica noted that the fastest Xeon processors could retain an advantage in raw clock rate or single-threaded performance. Its August 2019 analysis also disclosed that Ars did not have review hardware and relied on benchmark data supplied by Phoronix. That context matters when weighing the article alongside vendor launch claims. See Ars Technica’s August 2019 analysis.
ServeTheHome’s August 7, 2019 launch-era EPYC 7002 review likewise treated Rome as a platform change involving cores, memory, and PCIe, rather than a core-count update alone. Its rankings and purchasing context describe the 2019 market, not current availability or present-day product comparisons.
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Compatibility and buying an EPYC 7002 system
Compatibility is board- and system-specific. AMD’s datasheet warns that some features on first-generation EPYC motherboard deployments require an OEM BIOS update, and that a second-generation motherboard is required for all available functionality. Before buying a processor for an existing server, confirm its exact CPU support, BIOS revision, socket, cooling, memory configuration, and any feature limitations with the motherboard or system OEM.
For most organizations, a validated complete server from an OEM or specialist integrator is easier to support than sourcing a bare CPU and assembling a platform. AMD’s launch announcement named HPE and Lenovo systems as available at launch, announced Dell systems as forthcoming, and discussed Cray adoption; those are historical partner statements and do not establish current inventory. A bare AMD EPYC 7742 processor is a server CPU, not a complete upgrade: verify motherboard and socket support, BIOS, cooling, memory, and the listing’s condition before purchase. Current stock is not established here.
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