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1. Define the workloads and product constraints first
Before choosing an architecture, identify the models and operating conditions the processor must support. “AI workloads” is too broad a target: a design tuned for batched datacenter inference may be a poor fit for a real-time vision device or intermittent edge sensor.
- Workload: Select representative models and operations, such as convolution, transformer, recommendation, vision or signal-processing workloads. Include mixed workloads if the product will run more than one class.
- Execution mode: Specify training, batch inference, real-time inference or intermittent sensing. These impose different demands on throughput, latency and power.
- Tensor and operating conditions: Record tensor shapes, batch sizes, expected concurrency and input patterns. These determine how much parallel work is available and how well a proposed design can keep its compute units busy.
- Numeric format and accuracy: Choose candidate formats such as FP32, FP16/BF16, INT8 or lower precision, then verify the effect on model accuracy. A faster format is useful only if it meets the application’s accuracy requirements.
- Deployment envelope: Set latency and throughput targets, power and thermal limits, memory capacity, area or bill-of-materials constraints, and where the product will run: edge, embedded or datacenter.
These inputs form the workload specification. Keep it representative of deployment rather than relying on a single convenient model or tensor shape.
2. Compare architecture families against that specification
Evaluate candidate processors by workload fit, programmability, numeric-format support, memory hierarchy, interconnect, software ecosystem and lifecycle cost. The IEEE Standards Association’s active P1960 project describes ML hardware across edge devices and data-center servers, including CPUs, GPUs, FPGAs, specialized processors, accelerators, memory, storage and communications interconnects.
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| Candidate | Questions to evaluate |
|---|---|
| CPU | Can general-purpose execution and the available software handle the required operators and latency? Which tasks should remain on general-purpose cores even if specialized compute is added? |
| GPU | Does the workload expose enough parallelism to use the processor effectively? Check precision support, memory behavior and the software stack against the target models. |
| FPGA | Can configurable logic and the available development flow meet the workload and product constraints? Include implementation effort and the programming model in the comparison. |
| ASIC or NPU | Can a specialized design deliver the needed workload performance within area, power and memory limits? Consider software maturity and the cost of supporting changes in models or requirements. |
| Heterogeneous design | Can multiple compute engines be partitioned effectively, with clear compiler/runtime interfaces and manageable data transfers between them? |
This comparison is a screening step, not a ranking. The best candidate depends on the stated workload and product constraints; a nominally faster architecture may lose once memory traffic, utilization, software work or lifecycle cost is included.
3. Partition hardware and software together
Decide which operators and dataflows belong on specialized engines, which should stay on general-purpose cores, and how work and data move between them. Define compiler and runtime interfaces early so the intended mapping can be expressed, scheduled and measured.
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AMD’s Versal design methodology in UG1504 provides a concrete example of this sequence: application mapping and design partitioning are followed by planning for system compute, memory and data movement, throughput and latency, and power. That ordering is useful because a compute partition cannot be judged in isolation from the system needed to feed and coordinate it.
- Identify the operators that dominate the target applications and the engines suited to them.
- Decide how operators and data are assigned across specialized engines and general-purpose cores.
- Specify compiler/runtime responsibilities, including how mapped work is launched and coordinated.
- Account for communication, synchronization and memory access at partition boundaries.
4. Treat data movement as a first-class design limit
Compute units need data at the right place and time. An accelerator can have ample arithmetic capacity yet fail to sustain useful work if data cannot be delivered efficiently. A 2025 ACM Computing Surveys review identifies off-chip DRAM access as a common energy and latency cost in accelerators.
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During architecture design, account for on-chip SRAM or buffers, tiling, data reuse, compression, sparsity, DMA transfers, network-on-chip (NoC) bandwidth and DRAM traffic. These choices interact: a tile that improves reuse must fit the available storage, while a transfer schedule must serve the compute engines without creating a bandwidth bottleneck.
- On-chip capacity: Can the buffers hold the working sets or tiles needed for the target dataflow?
- Reuse: Can data be used multiple times on chip before another off-chip transfer is needed?
- Bandwidth and connectivity: Can memory and the NoC serve the required traffic at the same time?
- Transfer cost: What latency and energy are added by movement between DRAM, on-chip storage and compute engines?
- Compression and sparsity: Do the target models and implementation support these techniques, and are their effects reflected in the evaluated workload?
5. Explore the design space before committing to implementation
Use analytical or trace-based estimators to compare candidate array sizes, dataflows, numeric formats, memory configurations and sparsity assumptions. The objective is to identify promising trade-offs before committing to a detailed implementation, then carry those assumptions into prototype and application-level evaluation.
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MIT’s Accelergy is an architecture-level energy-estimation methodology intended for rapid accelerator design-space exploration. It can inform energy comparisons among candidate designs; it does not replace measurement of a complete application on a prototype or production system.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.6. Validate complete applications, not just peak arithmetic
ITU-T F.748.11 (2020) establishes an evaluation benchmark framework and reference model set for cloud and mobile deep-neural-network chip processors executing training and inference workloads. ITU-T F.748.18 adds requirements to describe hardware and the evaluation environment, and says the benchmark configuration should match the mass-production version.
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For each reported result, identify the model and dataset; compiler and runtime; clocks and batch size; numeric precision; cooling conditions; power-measurement boundary; and whether the result comes from simulation, a prototype or production silicon. Without those details, readers cannot tell what a performance or efficiency number represents or whether it applies to their workload.
7. Use a multi-objective scorecard to choose and iterate
Track trade-offs rather than selecting a winner from one headline metric. Keep a Pareto front: designs on it offer distinct combinations of objectives, and improving one objective may require sacrificing another.
- Performance: Measure latency—including tail latency where it matters—and sustained throughput, not only peak arithmetic.
- Energy: Track energy per inference or task alongside TOPS/W. ITU-T’s 2022 guidance describes energy efficiency as the ratio of AI computing power to electric power assumption; in a design comparison, make the workload and power boundary explicit.
- Resources: Record area, memory capacity and bandwidth, and thermal limits.
- Practicality: Include utilization, programmability, software maturity, updateability, yield and development risk.
TOPS (tera-operations per second) describes an operations-rate figure, while TOPS/W relates AI computing power to electric power. Neither is a self-explanatory ranking: the model, precision, benchmark configuration and power boundary matter. For scale, a 2025 ACM Computing Surveys review reports one accelerator example at up to 149 TOPS and 12.37 TOPS/W. Those are figures for that reviewed example, not a universal comparison or a prediction for another design.
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