The Tool Desk
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Where AI can help in design verification
The strongest practical role for AI is assistance around an established verification process. It can produce candidate artifacts or help engineers navigate results, while the existing simulator, formal engine, regression system, and human review remain part of the verification chain.
Setup and glue code
AI can help draft or adapt scripts, extract interface information from RTL, generate wrappers, and connect repeated steps in a flow. A 2025 conference paper by AMD-affiliated authors describes a Python framework using AI assistance for setup, interface generation, and regression analysis. That paper documents a workflow, not a general measure of accuracy or productivity: the reported conference paper.
Candidate assertions and properties
An assistant can turn a clearly stated behavior into a candidate SystemVerilog assertion or property. In the AMD-authored workflow, verification engineers reviewed generated properties before checking them with Synopsys VC Formal. This is a useful pattern—generate, review, then validate—not evidence that prompts routinely produce correct properties without oversight. The IEEE’s IEEE 1800-2023 SystemVerilog standard covers language features used in verification, including assertions, testbenches, coverage, and constrained-random verification.
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Test ideas and coverage exploration
AI can suggest test scenarios or help explore ways to exercise a design, but these remain candidate ideas. DFKI’s 2024 review surveys LLM approaches to hardware verification and discusses property consistency; Siemens also describes AI capabilities spanning simulation and debug. Neither description means that generated tests guarantee requirement completeness. Coverage must be interpreted according to the metric and model being used.
Regression triage and workflow coordination
AI can summarize logs, route results, or help identify relevant failures in a large regression. In the 2025 AMD-authored example, regression results were sent to test owners. The report supports assistance with handling results; it does not show that AI independently diagnosed and resolved every failure.
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Tool orchestration and EDA research
Vendors are adding AI features to broader EDA workflows. Siemens describes Questa One across simulation, debug, design creation, static and formal verification, and verification IP. Its performance or productivity figures are vendor claims; the available evidence does not establish an independent benchmark methodology. NVIDIA’s research group lists Bayesian optimization, reinforcement learning, and generative AI among methods studied for difficult EDA problems, including work from RTL through verification. That describes a research program, not proof that every method is production-ready for verification.
Where AI is unreliable or cannot replace an engineer
Unreviewed generated RTL, tests, or properties
Generated code can look plausible and still be wrong. DFKI’s 2024 publication identifies LLM non-determinism and limited capabilities as reasons generated hardware designs may contain bugs and generated properties may be incorrect. Treat outputs as drafts, not trusted verification assets.
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Ambiguous requirements and the verification oracle
A simulator or formal engine answers questions encoded in its inputs and model. If a requirement is incomplete, or an assertion captures the wrong interpretation, a passing result does not prove the intended behavior. AI cannot supply missing design intent merely by producing syntactically valid properties; engineers must define the behavior, assumptions, constraints, and relevant corner cases.
Coverage as a proxy for correctness
Coverage is evidence about the activity or cases measured by a particular coverage model; it is not, by itself, proof that every requirement or behavior has been verified. Say which measure is being used—such as code, functional, or assertion coverage—and what it does not capture. IEEE 1800-2023 supports multiple verification constructs, but choosing a meaningful coverage goal remains a verification-planning task.
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Vendor claims as independent evidence
Product pages can establish what a vendor says its tools do, but advertised speed or productivity gains should not be presented as neutral benchmark results unless independent measurement supports them. For example, Siemens’ Questa One claims should be attributed to Siemens rather than generalized to AI-assisted verification as a whole: Questa One product information.
A practical workflow for using AI safely
- Establish the verification basis. Start with a human-owned specification, verification plan, interface definitions, assumptions, and risk priorities.
- Request bounded drafts. Use AI for a specific task—such as a setup script, candidate assertion, or test idea—and provide only design context approved for that tool.
- Review semantics. Check reset behavior, clocking, corner cases, assumptions, and whether a property could pass vacuously or omit the behavior it was meant to express.
- Validate in the existing flow. Run reviewed artifacts through the organization’s simulator, formal engine, regression, and coverage processes. Keep logs and traceability between artifacts and requirements.
- Interpret results narrowly. A failure is a lead to investigate; a pass establishes only what the chosen model, constraints, properties, and checks actually cover.
- Govern design data. Decide what RTL, specifications, and logs may be sent to an AI service, and review retention, access, and intellectual-property terms before use.
How to evaluate AI verification tools
Compare tools by the work they perform and by how their outputs enter your existing verification process—not by the label “AI.” Distinguish conventional EDA flows, AI-assisted features embedded in commercial tools, and general-purpose or specialized LLM assistants used alongside those tools.
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| Evaluation question | What to establish |
|---|---|
| Task scope | Does it draft scripts, generate tests or assertions, assist debug, analyze regressions, or orchestrate tools? |
| Evidence quality | Is a claimed benefit supported by an independent benchmark, a vendor statement, or a single reported workflow? Do not treat these as equivalent. |
| Validation path | Can outputs be checked in your existing simulation and formal tools, with review and reproducible logs? |
| Data handling | Where are RTL and logs processed? What retention, access-control, and IP terms apply? |
| Traceability | Can engineers approve and version generated artifacts and link them to requirements? |
| Integration and cost | Confirm supported EDA tools, deployment model, licensing, compute needs, and maintenance directly with the provider; these details are not established for specific products here. |
Governance is part of the engineering decision
AI use can expose proprietary RTL, specifications, and debug logs, so data controls matter alongside technical validation. IEEE P4102 is an active project, approved on 2026-03-26, intended to develop guidance for AI use in electronic-systems and integrated-circuit development. Its stated scope includes privacy, intellectual property rights, information security, regulation, compliance testing, and workflow practices. It is a project, not a completed standard: IEEE P4102 project information.
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