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Texas Instruments described its 45-nm process in June 2006 as a mix of manufacturing techniques and power-management methods intended for mobile chips, DSPs and other designs. In February 2008, EE Times reported that TI was sampling a 45-nm 3.5G baseband and multimedia processor built around that generation of technology. The announcements gave different performance and power comparisons, so those figures should be read as dated company claims—not as independently verified, directly comparable test results.
What did TI reveal about its 45-nm process?
On June 12, 2006, TI outlined a 45-nm semiconductor process ahead of the Symposium on VLSI Technology. The company presented it not as one fixed recipe, but as a family of options aimed at different priorities: low-power mobile use, mid-range DSP and communications infrastructure ASICs, and highest performance. TI said strain techniques—including its first use of silicon-germanium in its strain application—would be used across the versions.
TI reported an SRAM cell area of 0.24 square microns, which it said it believed was up to 30% smaller than other 45-nm SRAM cells announced at the time. Both the cell size and the comparison were company-reported figures.
How did TI’s 45-nm process lower power and improve density?
Immersion lithography
TI said 193-nm immersion photolithography would support density improvements. In immersion lithography, a thin liquid layer sits between the lens and wafer during exposure, enabling finer patterning than dry lithography at the same wavelength. The announcement described this as a process capability, not a standalone performance test.
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Strained silicon and dielectric
The company described strain techniques to improve transistor performance and said its ultra-low-k dielectric had a k value of 2.5. TI reported that the dielectric reduced interconnect capacitance by 10%. These were figures in its June 2006 release.
Power and gate choices
TI also emphasized design methods alongside fabrication: its later 2008 disclosure described adaptive dynamic voltage adjustment, segmentation of on-chip memory, and an upgraded SmartReflex implementation with proprietary additions. These methods are distinct from the lithography and materials used to make the transistors.
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TI did not say that every 45-nm variant used a high-k metal-gate stack. In June 2006, EE Times reported that conventional nitrided silicon dioxide and polysilicon gates would be used for low-standby-power and high-performance processes, while metal-gate and high-k choices remained separate roadmap decisions. EE Times’ June 12, 2006 report on TI’s high-k plans gives that distinction.
What performance and power figures did TI claim?
The figures changed between the two announcements and have different contexts. Neither source provides a shared test protocol or independent validation that would reconcile them.
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| Announcement | Reported comparison | Qualification |
|---|---|---|
| TI, June 2006 | 30% better performance and 40% lower power | TI’s process/SoC capability claims relative to the preceding generation, as stated in its release. |
| TI, June 2006 | Up to 30% improvement in device speed; up to 30% longer cell-phone standby time | Company estimates of prospective outcomes, not independently measured results. |
| EE Times reporting on TI, February 2008 | 55% higher performance and 63% lower power versus 65 nm | A reported company comparison; the article does not supply an independent benchmark method. |
The June 2006 figures appear in TI’s press release reproduced by Chron/PRNewswire. The later figures were reported by EE Times on February 5, 2008. Because the sources do not establish the same baseline or measurement conditions, the later percentages should not be treated as a like-for-like update to the earlier ones.
What was TI’s first 45-nm mobile processor?
EE Times reported on February 5, 2008, that TI was sampling its first 45-nm 3.5G baseband and multimedia processor. The reported chip combined an ARM11 processor, TI’s TMS320C55 DSP, an image signal processor and handset analog functions, including an RF codec. The report described the process as mixed-signal and gave the package dimensions as 12 by 12 mm.
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- The LM567CN LM567 are tone decoders designed to provide a saturated transistor switch to ground when an input signal is present within the passband
- 20 to 1 Frequency Range With an External Resistor, Logic Compatible Output With 100-mA Current Sinking Capability
- Bandwidth Adjustable From 0 to 14%, High Rejection of Out of Band Signals and Noise
- Immunity to False Signals, Highly Stable Center Frequency
- Center Frequency Adjustable from 0.01 Hz to 500 kHz, Example Applications: Touch Tone Decoding, Precision Oscillator, Frequency Monitoring and Control, Wide Band FSK Demodulation, Ultrasonic Controls, Carrier Current Remote Controls, Communications Paging Decoders
TI senior vice president of silicon technology Hans Stork connected density increases with potential handset features in a statement reported by EE Times in June 2006: “The doubling in transistor density [compared with 65 nm] means we can add functionality, to support more standards in mobile phones, for multimedia or for watching higher-quality video,” Stork said.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Where was the 45-nm chip made?
TI’s 2006 release said its manufacturing plan used 300-mm wafers at its DMOS6 facility in Dallas. It forecast samples of a first system-on-chip in 2007 and initial production in mid-2008; those dates were plans announced in 2006, not confirmation that production followed that schedule.
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- The LM567CN LM567 are tone decoders designed to provide a saturated transistor switch to ground when an input signal is present within the passband
- 20 to 1 Frequency Range With an External Resistor, Logic Compatible Output With 100-mA Current Sinking Capability
- Bandwidth Adjustable From 0 to 14%, High Rejection of Out of Band Signals and Noise
- Immunity to False Signals, Highly Stable Center Frequency
- Center Frequency Adjustable from 0.01 Hz to 500 kHz, Example Applications: Touch Tone Decoding, Precision Oscillator, Frequency Monitoring and Control, Wide Band FSK Demodulation, Ultrasonic Controls, Carrier Current Remote Controls, Communications Paging Decoders
The February 2008 EE Times account says the specific 3.5G processor was designed by TI and fabricated by a foundry, but does not name the foundry. The reviewed accounts do not establish whether or how the DMOS6 plan related to fabrication of that processor.
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