Reducing FPGA block RAM (BRAM) use is a tradeoff, not a matter of choosing one universally best setting. A denser mapping can save BRAMs but add logic and threaten timing; a mapping with less muxing or shallower cascades may improve timing while using more active resources. Adam Taylor’s MicroZed Chronicles example shows the tradeoff with a 6K-by-256 memory, while current Vivado documentation places BRAM optimization in the default opt_design flow.
How BRAM width and depth affect a memory mapping
A logical memory has a depth (the number of addressable words) and a width (the bits in each word). FPGA BRAM primitives offer configurable width/depth combinations, so the way a design’s logical memory is divided across those primitives affects block count, extra logic, timing, and power.
Taylor’s article describes Seven Series and UltraScale+ BRAM structures as storing 36 Kb, configurable either as two 18 Kb RAMs or one 36 Kb RAM. For the 36 Kb structure, it gives configurations from 32K-by-1 through 1K-by-36; for an 18 Kb structure, from 18K-by-1 through 1K-by-18. These are the families and configurations discussed in that article, not a guarantee that BRAM primitives are identical across every AMD FPGA generation. Read Taylor’s MicroZed Chronicles article.
What the 6K-by-256 example shows
The article compares two illustrative mappings for a logical 6K-by-256 memory. The counts are the article’s examples, not independent benchmark results; it does not provide measured timing or power deltas.
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| Mapping | BRAM configuration and count | Tradeoff described in the article |
|---|---|---|
| Performance-oriented default | 64 BRAMs configured as 8K-by-4 | Avoids multiplexing in the same way as the denser decomposition, but uses more BRAMs. |
| More resource-efficient decomposition | Seven 1K-by-36 BRAMs replicated six times for depth, plus an 8K-by-4 memory for the last four data bits: 43 BRAMs total | Uses fewer BRAMs and is described as reducing power dissipation, but needs additional logic that can affect timing. |
The example’s 43-BRAM mapping saves 21 blocks compared with the 64-BRAM mapping, but the source gives no percentage power saving or timing penalty. Whether the denser arrangement is worthwhile depends on the design’s timing margin, surrounding logic, and implementation results.
What ram_decomp and cascade_height do
Use RAM decomposition to explore a denser mapping
Taylor presents RAM_decomposition with the value power as a way to request a more resource- and power-oriented memory decomposition. The article’s XDC example is:
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set_property ram_decomp power [get_cells myram]The article says the constraint can also be applied in RTL. Its qualitative tradeoff is fewer BRAMs and lower power, at the cost of extra logic that may affect timing.
Use cascade height to control built-in multiplexing
The article describes cascade_height as controlling the number of built-in multiplexers used within larger RAM structures. Its example sets the height to one:
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set_property cascade_height 1 [get_cells myram]In the article’s comparison, reducing cascade height can improve performance, but may cause more than one RAM to be active at a time and reduce power efficiency. It illustrates combining decomposition and cascade height with an 8K-by-36 memory as a way to retain single-RAM activity while limiting cascading. Treat this as device- and tool-era guidance: confirm that the property names and behavior are supported for your target FPGA and Vivado release.
How this fits into Vivado’s current implementation flow
Manual memory constraints are only one part of the decision. AMD’s Vivado Design Suite User Guide: Implementation (UG904), version 2026.1, released June 23, 2026, identifies opt_design as the logic optimization stage and lists -bram_power_opt among its options. The guide says BRAM optimization normally runs by default; explicitly supplying optimization options is one way to skip it. See AMD UG904’s opt_design documentation.
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AMD’s Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997), also version 2026.1 and released June 23, 2026, says block RAM optimization runs in the Default Opt Design setting during implementation. It describes enabling Power Opt Design and running implementation with power optimization enabled. See AMD UG997’s Block RAM Optimization guidance.
AMD’s Tcl Command Reference Guide (UG835), version 2024.1, released May 30, 2024, likewise says BRAM power optimizations are performed by default with opt_design. It describes configuring cells with set_power_opt and notes that running power optimization before placement permits more optimizations, while optimization after placement is more constrained by timing preservation. Check the documentation matching the installed Vivado version rather than assuming behavior is unchanged. See AMD UG835’s set_power_opt reference.
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A practical way to decide whether a constraint helps
- Establish the baseline. Run synthesis and implementation for the target FPGA and Vivado version without changing the memory constraints. Record BRAM count, timing results, and power-estimation results if available.
- Try one change at a time. Test a decomposition or cascade-height setting on the intended memory, using the article’s examples only if those properties are valid for your target and release.
- Compare reports, not just BRAM count. Check whether the mapping changes the number and configuration of RAM blocks, introduces additional logic, affects timing, or changes power estimates.
- Keep the setting only if it meets the design’s goals. A smaller BRAM count is not an improvement if the added logic causes timing failure or the power outcome is worse for the actual design.
A third-party-hosted copy of AMD UG904 version 2021.1 describes BRAM power-optimization actions including changing WRITE_MODE to NO_CHANGE on unread ports of true dual-port RAMs and applying intelligent clock gating to BRAM outputs. That description is specific to the 2021.1 guide excerpt; AMD’s 2026.1 excerpts cited above establish default flow behavior but do not independently restate those mechanisms. See the UG904 2021.1 guide.
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