DUV lithography can help make chip patterns finer than a single exposure can reliably print by dividing a dense pattern into simpler ones—or by using deposited sidewall spacers to multiply a coarser pattern. Those patterns are then combined and transferred into the wafer. The gain is denser features; the trade-off is more exposures or process steps, plus tighter alignment and process control.
Why can 193 nm DUV make features smaller than its wavelength?
Lithography is a pattern-transfer process. A reticle carries a pattern, projection optics reduce and focus its image onto photoresist on a silicon wafer, and later processing transfers the resist pattern into the material stack. Chipmaking repeats this process across many layers. A process node name does not correspond to one feature size, and different layers on the same chip can use different patterning approaches. ASML’s explanation of lithography describes the optical patterning process.
Wavelength matters, but it is not the only factor that determines resolution. The Rayleigh criterion also depends on numerical aperture (NA) and a process factor. Immersion lithography puts water between the projection lens and wafer to increase NA. ASML says its highest-resolution DUV systems reach NA 1.35; that figure describes those systems, not every DUV scanner. ASML’s lithography principles explain the role of wavelength and NA.
Even with these techniques, a dense layout can exceed what one exposure can reproduce with sufficient fidelity. Multi-patterning addresses that limit by asking each exposure or process step to create a simpler part of the final pattern.
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How does double patterning work?
LELE: print and etch two pattern subsets
Litho-etch-litho-etch (LELE) divides a dense layout into two simpler subsets. One subset is exposed and etched; a second exposure and etch forms the other. Together, the transferred patterns create a denser arrangement than either exposure would make alone.
Because the two patterns are made separately, their relative placement—called overlay—matters. The layout must also be decomposed so that shapes can be assigned to each exposure, and the process must integrate both sequences successfully. ASML describes this general approach as splitting complex patterns into simpler ones and printing them separately. Its 2025 annual report gives that description in its discussion of DUV and multi-patterning.
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SADP: use sidewalls to create additional lines
Self-aligned double patterning (SADP) starts with a lithographically printed core, often called a mandrel. A conformal material is deposited over it and etched back, leaving material along the core’s sidewalls. When the core is removed, the remaining spacers form additional lines that can be transferred into the layer below.
Instead of aligning two separately exposed line patterns as in LELE, SADP uses the original core to position the spacer lines. It still needs deposition, etching, core removal and pattern transfer, all of which must be controlled. Imec’s explanation of self-aligned patterning describes spacer formation and its role in creating denser line arrays.
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SAQP: repeat the spacer cycle
Self-aligned quadruple patterning (SAQP) extends the idea: the first spacers become a new core, and another spacer cycle adds lines. Imec describes the sequence as turning each initial line into a result with four times the line-pattern density. This refers to pitch multiplication in a regular array—not features becoming four times smaller in every dimension. Line ends and irregular shapes need additional block or cut patterning.
For a dated example, imec reported a 2017 demonstration combining SAQP lines with EUV block exposure: 32 nm pitch metal-2 lines with a 16 nm half-pitch. That is a specific demonstration, not a universal production specification or a description of every process node. Imec’s account of the demonstration describes the patterning flow.
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Why does multi-patterning add steps and control challenges?
Breaking a pattern into parts can overcome a single exposure’s resolution limit, but it makes the overall process more involved. LELE adds separate lithography and etch sequences; SADP and SAQP add deposition, spacer etch and core-removal operations. A greater number of operations creates more points where variation can affect the final pattern.
- Overlay: Separately exposed patterns must land in the intended relative positions, particularly in LELE.
- Critical dimensions: Line widths and spacing must stay within target across the different populations of lines produced by spacer cycles.
- Pattern shape: Spacer multiplication is suited to regular line arrays, but cuts, blocks and irregular features require additional patterning.
- Integration: Masks, exposures, deposition, etch, metrology and pattern transfer must work together for a given layer.
Imec and Nova have described scatterometry development for SAQP process control, aimed at identifying contributors to critical-dimension variation among line populations. Their account of the work illustrates why measurement is part of the patterning challenge, not an afterthought. ASML also describes computational lithography as optimizing masks, scanners and process conditions to account for physical and chemical effects and improve manufacturability. ASML’s computational lithography overview explains that role.
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Does EUV replace DUV multi-patterning?
No single technology replaces the others across every chip layer. EUV uses a shorter wavelength than DUV and can print some patterns in one exposure that would need multiple patterning steps with DUV. In its 2025 annual report, ASML notes that EUV can reduce steps in such cases, while also noting that EUV systems consume more power. That vendor comparison does not establish a universal cost or lifecycle winner. ASML’s 2025 annual report discusses the trade-off.
EUV does not eliminate every use of multi-patterning, and hybrid flows can combine methods on the same layer. In imec’s N5 back-end-of-line demonstration, immersion-based SAQP formed metal lines and EUV exposure formed block features before etch and metallization. A chip or process node therefore should not be described simply as “DUV” or “EUV” without specifying the layer and patterning flow. Imec’s demonstration account gives this hybrid example.
Imec reported 20 nm-pitch single-print patterns in High-NA EUV demonstrations in 2025. These are research results, not proof that all such patterns are already used in volume production. Imec’s report on the demonstration describes the milestone. For any given layer, the choice among DUV multi-patterning, EUV or a hybrid depends on geometry, patterning performance, process complexity, control requirements, throughput and cost of ownership. The available comparisons do not establish one numeric ranking that applies across fabs and layers. Imec’s comparison of patterning options discusses these evaluation axes.
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