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Memory bandwidth is the rate at which data moves between a processor and its local memory. AI accelerators need high bandwidth because their compute units must continually receive model weights, inputs and intermediate results. If moving data is the bottleneck, adding more arithmetic capacity alone may not make a workload faster.
Memory bandwidth is speed; memory capacity is space
Bandwidth is a data-transfer rate, usually measured in bytes per second. Capacity is the amount of data memory can hold, typically measured in gigabytes or gibibytes. They answer different questions: how much data fits locally, and how quickly that data can be delivered to the processor.
That distinction matters for AI hardware. A model may fit in a GPU’s memory but still run slowly if the processor cannot receive data quickly enough to keep its compute units occupied. Conversely, high bandwidth does not help if the required data cannot fit in memory or if another part of the system is the limiting factor.
Why AI workloads can demand high bandwidth
AI operations perform arithmetic on model weights, input data and intermediate values called activations. Those values have to be fetched, reused and sometimes written back. When the workload moves a lot of data relative to the amount of computation it performs, the processor may spend time waiting for memory instead of doing arithmetic.
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A kitchen analogy helps: compute units are cooks, memory is the pantry, and bandwidth is the speed of the route bringing ingredients to the workstations. A larger pantry represents more capacity; a faster route represents more bandwidth. The analogy has limits, because real performance also depends on reuse, caches, access patterns, compute throughput and communication with other chips.
Inference and training do not have one universal bottleneck
In language-model inference, repeatedly accessing model weights can make memory bandwidth important, particularly in memory-bound phases. The balance varies with the model, batch size, sequence length, numerical precision and system design. Training can also be limited by memory behavior, but the limiting operation can change with the workload and setup. It is not accurate to say every AI task is memory-bound—or that more bandwidth alone guarantees faster training or inference.
NVIDIA says the H200’s higher bandwidth can relieve bottlenecks in memory-bandwidth-bound portions of workloads and enable better Tensor Core utilization. That is the vendor’s explanation of a potential benefit, not a universal promise of application speedup. NVIDIA’s H200 technical blog discusses that claim.
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Memory is part of a hierarchy
Accelerators do not rely on one uniform pool of memory. Data can be held close to the compute units in registers, caches or other on-chip storage, or kept in off-chip high-bandwidth memory (HBM). These levels differ in capacity and transfer characteristics. Reusing data close to the compute units can reduce trips to HBM, while inefficient access patterns can waste even a high-bandwidth memory system.
Google Cloud’s TPU7x documentation describes HBM alongside a smaller on-chip SRAM called vector memory (VMEM), whose bandwidth to the matrix unit is higher than HBM’s. This illustrates why a single published HBM figure does not describe every route data takes inside an accelerator. Google Cloud’s TPU7x specifications describe its memory hierarchy.
Published bandwidth figures are specifications, not benchmark results
These vendor-published figures show how capacity and bandwidth appear in accelerator specifications. They refer to particular configurations; they are not results from a controlled comparison between architectures.
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| Accelerator configuration | Published local-memory bandwidth | Published memory capacity | Source and qualification |
|---|---|---|---|
| NVIDIA H100 SXM | 3.35 TB/s | 80 GB HBM3 | NVIDIA HGX reference table, accessed 2026; SXM configuration |
| NVIDIA H200 SXM | 4.8 TB/s | 141 GB HBM3e | NVIDIA HGX reference table, accessed 2026; SXM configuration |
| NVIDIA B200 SXM | Up to 8 TB/s | 180 GB HBM3e | NVIDIA HGX reference table, accessed 2026; SXM configuration |
| Google TPU7x (Ironwood) | 7,380 GB/s per chip | 192 GiB HBM per chip | Google Cloud TPU7x specification table, accessed 2026; Google also describes bandwidth as approximately 7.37 TB/s |
Sources: NVIDIA HGX component reference and Google Cloud TPU7x specifications. The figures are published specifications, not independently measured workload results. The units and architectures differ, so they should not be read as a head-to-head performance ranking.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to tell whether bandwidth matters for a workload
Memory bandwidth is one possible throughput ceiling alongside compute capacity and inter-chip communication. Google Cloud identifies compute capacity, local HBM bandwidth and inter-chip network bandwidth as three primary accelerator constraints. Its benchmarking guide recommends roofline analysis to relate computation to data movement. In Google Cloud’s words, “A roofline analysis (or roofline model) can provide you with a visualization to analyze the operational intensity (OI) of different system components and how well specific designs suit specific platforms.” Google Cloud’s AI accelerator performance and benchmarking guide explains this approach.
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Operational intensity describes how much computation a workload performs for the data it moves. A workload with relatively little computation per byte moved is more likely to hit a memory limit; one with substantial computation per byte may instead be limited by compute throughput. Access patterns and reuse matter too: poor access or little reuse can constrain performance even when peak bandwidth is high.
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When comparing systems for a real workload, assess the full set of constraints rather than ranking by one specification:
- Memory capacity: whether the required data can reside locally.
- Memory bandwidth: how quickly data can move between local memory and compute.
- Compute throughput: arithmetic capability, accounting for data type and whether a quoted figure is dense or sparse.
- Inter-chip bandwidth: how quickly accelerators exchange data in distributed work.
- Workload behavior: operational intensity, reuse, access pattern, batch and sequence configuration, and measured performance.
Peak bandwidth is a useful hardware specification, not a guarantee of application speed. The practical check is performance on the workload and configuration that matter to you.
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