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Choose a semiconductor foundry by matching your chip’s workload, process, package, engineering needs, production schedule, and supply-chain constraints—not by picking the smallest node name. For an AI accelerator, HBM and advanced packaging may matter as much as the wafer process. For a robotics chip, the right choice depends on its actual mix of compute, sensor and actuator interfaces, memory, power, thermal limits, reliability, and volume.
Start by turning the product into manufacturing requirements
Before contacting foundries, write down what the chip must do and what the finished product can tolerate. Separate hard requirements from targets that could change if they add substantial cost, risk, or delay. This gives each potential supplier the same design brief and makes proposals easier to compare.
- Workload: target throughput, latency, and the software or algorithms the chip must support.
- Power and physical limits: power envelope, target die area, acceptable package dimensions, cooling approach, and operating temperature.
- Memory and connectivity: bandwidth, memory type, I/O, and whether the design needs HBM, chiplets, or high-speed die-to-die links.
- Product environment: reliability requirements and, for robotics, the sensor and actuator interfaces and conditions where the product will operate.
- Business plan: expected unit volumes by year, first-silicon date, and production launch date.
A robotics product might need compute for perception alongside real-time control, multiple sensor interfaces, or operation across a wide temperature range. Those requirements should drive the process decision; the fact that the product is a robot does not, on its own, mean it needs a leading-edge node.
Which process family fits the chip?
Ask which candidate processes can meet the design’s performance, power, and area targets while also supporting any specialty requirements, such as analog or mixed-signal circuits, nonvolatile memory, high voltage, or automotive and industrial reliability. A mature process may be a better fit if it offers the features the design needs at lower cost or with less process risk. A leading-edge process may make sense when density or performance justifies its costs and design demands.
#1 Best Overall
- Tang Mega 138K Pro Dock development board kit uses GW5AST FPGA as the main controller chip, the chip has 138240 LUTs and REGs, and a series of resources such as 12 PLLs to meet a variety of functional requirements, integrated 800MHz RISC-V hardcore processor, and BTB connectors to connect with the backplane.
- The Tang Mega 138K Pro Dock single board computer is equipped with Gigabit Ethernet, SFP+ and PCle interfaces, which are suitable for learning and verifying high speed FPGA communication. It is also equipped with multiple camera interfaces and display interfaces, which can be easily used for image acquisition and display.
- Tang Mega 138K Pro Dock single board computer on board rich peripheral interfaces, hard-core compatible with PCle 3.0 external lead x4 interface, a single transmission rate of up to 8GT / s (GT = Gigabyte Transfers), through the PCle x4 interface can realize up to 32GT / s high-speed data transfer. The core board measures 50mm x 70mm.
- Tang Mega 138K Pro Dock development board can be connected to the standard SFP/SFP + fiber optic transceivers, each way the transmission rate of up to 10Gbps, so that FPGAs can also use high-speed fiber optic communication for stable and reliable, suitable for high-speed communications, protocol conversion, high-performance computing and other occasions.
- Provide core board package, customers can customize the design of the base board, not only can learn to customize the core board features, but also to facilitate industrial customers to directly embed the existing program to bring more diverse learning experience, more convenient development and integration.
Node names are vendor-defined labels, not directly comparable physical measurements or guarantees of a particular chip’s performance. A process comparison is meaningful only when it addresses the design’s actual workload, implementation, and constraints. Request the process design kit (PDK) and applicable design rules under the foundry’s access terms, and establish whether the process is available and mature enough for the planned schedule. A roadmap announcement is not proof of production readiness.
Use vendor performance figures as narrowly as they are presented. For example, TSMC states that its A16 process, compared with N2P, offers 8–10% higher speed at the same Vdd, 15–20% lower power at the same speed, and up to 1.10× chip density. These are TSMC’s comparisons between those named processes—not an independent benchmark or a general comparison between foundries. Ask for evidence relevant to your intended design before using such figures in a business case.
Can the design team use the process ecosystem?
A process is only a practical option if the team can design, verify, and sign off the chip on it. Evaluate the enablement package alongside the process itself.
Rank #2
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
- Design access: PDK availability, design rules, and the terms and timing for receiving them.
- Verification and signoff: DRC/LVS, extraction, signoff tools, and qualified EDA software versions.
- Reusable building blocks: availability and qualification of required memory and interface IP.
- Execution support: reference flows, prototyping or shuttle options, application-engineering access, and design-review support.
TSMC describes its Open Innovation Platform as providing design enablement and EDA certification. Samsung describes SAFE partner design enablement for HPC and AI. Those descriptions establish that the ecosystems exist; they do not confirm that a particular customer has access to a needed IP block or that its specific flow is qualified. Verify those details for your design before selecting a process.
For AI and chiplet designs, evaluate packaging and memory with the wafer process
If the chip uses HBM, chiplets, high-speed die-to-die links, or a large compute die, the package is part of the architecture—not a manufacturing detail to settle after choosing a wafer process. Ask each candidate how it supports the complete path from die through assembly and test.
- Which package architectures are supported, and what are the relevant interposer or bridge limits?
- What are the assembly and test flow, package-design tools, and known-good-die strategy?
- What guidance is available for thermal management and power delivery?
- What engineering support and package capacity can the supplier commit for the required dates and volumes?
TSMC describes CoWoS as 2.5D packaging for HPC and AI and says it is expanding capacity. Samsung describes heterogeneous integration that combines logic and HBM. These vendor capability statements do not establish customer-specific allocation, price, schedule, or yield. Ask for commitments and evidence that apply to the proposed design and production plan.
Rank #3
- Designed for students and beginners looking to understand Digital Logic, fundamentals of FPGAs
- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
- Expansion opportunities with four Pmod ports including 3 standard 12-pin Pmod ports and 1 dual
- Does NOT ship with micro USB cable
What should you verify about manufacturing readiness?
Request evidence tied to the process, package, and reliability requirements under consideration. Useful diligence includes relevant qualification status, production experience or reference evidence where available, yield-ramp assumptions, process controls, failure analysis, and the foundry’s procedures for notifying customers about changes. Establish what support is available during bring-up and how issues will be escalated.
TSMC describes process controls spanning front-end fabs and back-end manufacturing. Intel Foundry’s fact sheet describes a full-stack process and packaging offer and makes scale claims. Treat these as company descriptions, not independent rankings or proof of performance on your chip. Ask each supplier for evidence relevant to the specific process and package in its proposal.
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The vendor descriptions below can help form a shortlist, but they are not a like-for-like benchmark. Confirm current process maturity, design access, qualification, package availability, and capacity directly with each supplier for the proposed project.
Rank #4
- The best way to get started with FPGAs: Using a simple board with projects that build on eachother, now anyone can get started with FPGA development!
- Fun peripherals available: With 4 LEDs, 4 push-buttons, 7-segment display, USB connector, a VGA connector, and a PMOD (for expansion) you can have dozens of fun projects available to you out of the box!
- Works with Verilog and VHDL: No matter which programming language you want to get started with, the Go Board will work for you!
- No extra device required: Simply plug the Go Board into a USB port and go! Getting started with FPGAs has never been easier.
- Works with all operating systems: Windows, Mac, Linux
| Foundry | What its published materials describe | What to confirm for your project |
|---|---|---|
| TSMC | Engineering and process management from front-end fabs through back-end packaging; CoWoS 2.5D packaging positioned for HPC and AI; an Open Innovation Platform for design enablement and EDA certification. | Access to the required process, PDK, IP and qualified flows; relevant package configuration; engineering support; and project-specific allocation, price, schedule, and yield assumptions. |
| Samsung Foundry | HPC/AI process recommendations, HBM-oriented packaging, SAFE ecosystem enablement, and heterogeneous integration with described 2.5D production-qualified configurations. | Whether the proposed process and package are qualified and available for this design, plus customer access, capacity, schedule, and engineering support. |
| Intel Foundry | A full-stack foundry and packaging offer, with advanced-packaging scale claims in its fact sheet. | Evidence relevant to the proposed process and package, design enablement and IP, qualification, capacity, and commercial terms. |
These descriptions establish what the companies say they offer; they do not establish which one is the best fit. Public capability pages do not provide equivalent, independently measured yields, project prices, delivery schedules, or customer-specific capacity.
Compare written proposals on the same assumptions
Ask at least two credible candidates to price the same design assumptions. Compare the cost of usable, tested chips—not just the wafer price—and include the terms that determine whether the proposed schedule and volume are achievable.
- Engineering and mask charges, and the NRE payment schedule.
- Wafer price and wafer size, along with the assumptions used for gross and tested die yield.
- Package and test costs, including the proposed assembly flow.
- Minimum volumes, capacity reservations, and lead times.
- Cancellation and rescheduling terms, IP and confidentiality provisions, logistics, and currency.
Model expected cost per good packaged chip at realistic production volumes. Test how the economics change under different yield and schedule assumptions rather than treating a single forecast as certain. Public technology pages do not establish which supplier will be cheapest or fastest for a particular project; those answers require comparable, written, project-specific proposals.
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- [FPGA RISCV CPU] Tang Primer 25K Dock single board computer is a new generation of modular development board with onboard RISC-V soft core, 23K LUT4 FPGA GW5A RISCV CPU, supports MIPI 2.5Gbps Ethernet, and is equipped with a USB-JTAG debugger , 3x PMOD interface, 1x USB interface and 1x 40P pin header interface to facilitate FPGA programming.
- [PMOD Interface Module] The Tang Primer 25K Dock single board computer supports using the PMOD interface to connect simple modules such as HDMI modules, game controller modules and LED modules. It can also use the 40 PIN GPIO interface to connect SDRAM modules, dual DVP camera modules and other more complex functions. module.
- [Small Size, High integration] Tang Primer 25K Dock single board computer is a small, highly integrated FPGA development board. It only needs to provide a 5V power supply to the core board and correctly set the configuration pins. It can be applied to any space with limited space. scene.
- [Rich Peripheral Pins] Tang Primer 25K Dock development board integrates Gowin GW5A-LV25MG121, 64Mbit SPl FLASH, DC-DC power supply and BTB connector. Its core board leads to 76 GPIOs and 1 hard core 4lane MIPI line and 3 power outputs for users to use.
- [Application Scenarios] The Tang Primer 25K Dock development kit is equipped with a downloader and does not need to be connected to other downloaders for programming, making secondary development and programming easier. It can be widely used in FPGA education and teaching, game equipment, cameras, and security monitoring equipment wait
Include location, resilience, and regulatory constraints
Map the full manufacturing chain, not just the wafer fab. Identify where wafers, substrates and HBM are sourced, where assembly and test occur, how products will be shipped, and where the customers are located. Flag customer procurement rules, government-program conditions, export controls, security requirements, and other applicable restrictions early. The answer depends on the chip, counterparties, and destination; work through relevant obligations with qualified counsel and the foundries. The Congressional Research Service’s semiconductor supply-chain report provides broad U.S. context, not a determination of any individual company’s legal obligations.
Use a shortlist scorecard and ask for evidence
Compare candidate offers against the same priorities, recording both the answer and the evidence that supports it. Do not treat an unverified claim as equivalent to a written commitment or a qualified design flow.
- Process and design fit: relevant PPA evidence, specialty features, PDK readiness, IP, and signoff support.
- Package and memory: HBM, interposer or bridge architecture, die-to-die links, test flow, thermal and power delivery, and committed capacity.
- Manufacturing maturity: relevant qualification, production evidence, yield learning, process control, failure analysis, and change management.
- Commercial terms: good-die and packaged-chip cost, NRE, minimum volumes, reserved capacity, lead time, and contractual flexibility.
- Location and resilience: jurisdictions, supply-chain dependencies, logistics, and customer or program requirements.
- Engineering relationship: application-engineer access, response expectations, design reviews, and escalation path.
In technical and commercial reviews, make sure the team gets clear answers to these questions:
- Which available processes meet the workload, PPA, die-size, reliability, and cost constraints—and will they be in production on the required schedule?
- Which PDK, EDA versions, IP blocks, and signoff flows are available and qualified for this customer’s design?
- Which package and HBM configurations are supported, and what package capacity and engineering support can be committed?
- What are the comparable costs for NRE, masks, wafers, packaging, test, expected yield, minimum volume, and reserved capacity?
- What evidence supports the proposed yield and ramp schedule, and how will process changes and failures be handled?
- Which jurisdictions and supply-chain constraints apply to design access, wafer fabrication, assembly, and delivery?
A foundry should move forward on the shortlist when its evidence and written terms fit the product’s constraints—not simply because its node label, scale claim, or technology page sounds strongest.
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