IBM’s resistive-computing research could make some AI workloads faster or more energy-efficient by reducing the movement of data between memory and processors. But the most dramatic figures associated with the idea—up to 30,000 times higher performance and 84,000 giga-operations per second per watt—were conditional projections for a proposed design published in 2016, not results from a commercial chip. IBM later reported measurements from a fabricated analog chip, while its newer 3D designs remain simulation results. The “Positronic Brain” is a science-fiction metaphor, not a claim that IBM has built a brain-like mind.
What is resistive computing?
In a conventional computer, a processor often has to fetch neural-network weights from memory, use them in calculations, and move results onward. Repeatedly transporting large amounts of data takes time and energy. IBM’s analog in-memory computing research aims to reduce that burden by placing computation close to where the model’s weights are stored.
In an analog memory array, the conductance of each device can represent a weight. When voltages are applied across the array, electrical currents combine in ways that perform multiply-accumulate operations in parallel. These operations are central to matrix-vector multiplication, a recurring calculation in neural networks. The approach is intended to improve throughput and energy efficiency by limiting data movement; it does not eliminate the need for processors or digital circuitry.
Resistive devices and phase-change memory
“Resistive computing” can refer to work using devices whose resistance stores information, but IBM’s research also uses phase-change memory (PCM). PCM changes conductance by switching a material between amorphous and crystalline states. In resistive random-access memory (RRAM), a device’s resistance changes as a conductive filament forms or changes between electrodes. Both can encode values in memory devices, but they are different technologies, not interchangeable names for a single finished product.
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Why a practical chip is mixed-signal
Analog arrays are suited to certain dense matrix operations; other tasks still call for digital processing. IBM’s 64-tile PCM prototype combined its analog tiles with a global digital processing unit and a digital communication fabric. That arrangement matters: an analog array alone does not run every part of a modern AI model. A complete system must coordinate data, handle operations that are not well suited to analog computation, and account for non-ideal device behavior.
What has IBM actually demonstrated?
The evidence spans three distinct stages: a proposed architecture with modeled projections, a fabricated prototype with reported measurements, and newer hardware architectures evaluated in numerical simulations. Their figures describe different kinds of evidence and workloads, so they should not be read as competing results from a single benchmark.
| Work | Evidence and reported result | What the result does—and does not—show |
|---|---|---|
| Resistive processing unit (RPU) proposal, 2016 | PC Magazine’s May 2016 account described a proposed, densely tiled RPU system and projected up to 30,000 times the performance of then-current architectures and 84,000 giga-operations per second per watt. It also modeled a system with 100 tiles and a CPU core handling a network with up to 16 billion weights at 22 watts. | These were conditional projections for a design, not measured performance from a built product. The comparison is framed against architectures current at the time, not today’s hardware. |
| 64-tile PCM chip, reported in 2023 | IBM researchers reported 92.81% accuracy on CIFAR-10 and 400 GOPS/mm² for 8-bit input-output matrix multiplications. IBM said the area-normalized throughput was more than 15 times that of prior multi-core in-memory chips based on resistive memory, with comparable energy efficiency. | These are results for a fabricated mixed-signal prototype and specified tasks. GOPS/mm² is throughput per unit area, not an end-to-end application speedup or a general-purpose AI acceleration factor. |
| 3D analog in-memory MoE architecture, recent IBM work | IBM reports numerical simulations in which different mixture-of-experts (MoE) transformer experts are mapped to tiers of non-volatile memory. The simulated system showed higher throughput, area efficiency, and energy efficiency than commercially available GPUs for the models tested. | This is a simulation-based comparison for the tested models, not a measurement from a fabricated or shipping 3D accelerator. IBM’s described account does not give a single general-purpose speedup figure that can be compared directly with the 2016 projection or 2023 prototype metrics. |
The 2016 RPU numbers are the origin of the most dramatic acceleration claims. They should not be attached to the 2023 prototype or to IBM’s simulated 3D design. The prototype is evidence that analog in-memory inference hardware can be fabricated and measured; its CIFAR-10 accuracy and matrix-operation throughput are specific results, not proof that every AI task will run faster.
Can analog chips make AI faster?
They may accelerate the operations they are designed to handle, especially matrix calculations that dominate many neural-network workloads. Moving less data between memory and compute can also reduce energy spent on data transport. But a chip’s useful performance depends on the entire workload: how much computation maps to its analog arrays, what must run digitally, how results are communicated, and what accuracy and precision the application requires.
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Real analog devices do not behave as perfectly as mathematical models. Their variations and non-idealities affect the relationship between stored conductance and computation. IBM’s Analog Hardware Acceleration Kit (AIHWKit) provides device models and supports hardware-aware training, which lets researchers account for such behavior in an AI workflow. The repository describes AIHWKit as beta software under active development; it is a research toolkit, not an analog accelerator in itself.
Not every transformer operation maps neatly to analog
Transformer models include attention computations as well as matrix operations. IBM researchers have noted that attention involves nonlinear computation that is not straightforward to accelerate with analog in-memory hardware. IBM’s proposed mixed analog-digital neural processing unit for edge transformer inference, studied using MobileBERT, is an example of a hybrid approach. The reported competitive throughput and expected energy benefits are research findings and projections for possible uses such as cameras and automotive sensors, not evidence that those products currently contain IBM’s proposed unit.
What does “Positronic Brain” mean here?
Isaac Asimov’s Positronic Brain is fictional. The phrase works as a metaphor for computing inspired by selected ideas from neuroscience, but IBM’s approach is not a biological brain, a robot mind, or a machine that thinks as a human does. The engineering analogy is narrower: store model parameters in devices and compute near those stored values, rather than continually moving them between separate memory and processing units.
IBM’s brain-inspired projects are not all the same. Its analog PCM chips and RRAM research use memory-device properties for computation. IBM’s NorthPole project, by contrast, uses digital processing and captures brain-inspired mathematics in a different architecture. “Brain-inspired,” “analog AI,” and “resistive computing” therefore describe overlapping themes, not one technology or one product.
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Is IBM’s resistive AI chip available?
The IBM material described here establishes research prototypes, proposed designs, simulations, and research software; it does not establish consumer availability for the RPU proposal, 64-tile PCM prototype, or simulated 3D system. No launch date, retail price, or public access route for those chips is stated in the cited accounts, so it would be misleading to describe them as products readers can buy.
Researchers interested in exploring the concept can look at IBM’s Analog Hardware Acceleration Kit, an open-source Python toolkit that supports PyTorch workflows and models analog device behavior. Its repository labels the software beta and under active development, so its capabilities and maturity should be understood as those of a research tool rather than a finished hardware offering.
How to interpret IBM’s acceleration claims
- Check the evidence type. A modeled projection, a measurement on fabricated silicon, and a numerical simulation answer different questions.
- Keep the workload attached to the number. CIFAR-10 accuracy, matrix-multiplication throughput, and modeled transformer performance are not interchangeable benchmarks.
- Read the metric literally. Throughput per square millimeter is an area-normalized result, not a direct measure of application latency or overall system speed.
- Look for the system around the array. Digital processing, communication, precision limits, and operations such as attention affect whether an analog design helps a complete AI workload.
IBM’s work makes a serious case for exploring computation in memory as a way to reduce the cost of data movement. It also shows why the headline requires qualification: the spectacular RPU figures remain historical projections, the measured chip results are narrower prototype metrics, and the newest 3D claims are simulation-based. That is meaningful progress in AI hardware research, but it is not yet an Asimov-style brain or a demonstrated universal shortcut to faster AI.
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