Imec has announced a 7-bit slope ADC that samples at 175 billion samples per second (GS/s), targeting the electrical side of high-speed optical transceivers for data centers. The 5nm FinFET prototype uses 2,048 parallel channels and has a reported 250 × 250µm² core area and conversion energy of 2.2pJ per sample. Those are imec-reported prototype figures, not independent benchmark results.
What imec announced at ISSCC 2026
At the 2026 IEEE International Solid-State Circuits Conference (ISSCC), imec presented a 7-bit, 175GS/s massively time-interleaved slope ADC. Imec says its sampling speed ranks among the fastest reported for converters at a comparable resolution. The announcement describes a research prototype, not a commercially available component.
The reported implementation uses 5nm FinFET technology. Its core measures 250 × 250µm², and its conversion energy is 2.2pJ per sample. Imec does not state the prototype’s total power consumption in the announcement details summarized here, so the per-sample figure should not be treated as a total-power specification.
How the 2,048-channel slope ADC works
A slope ADC samples an input and compares it with a ramp whose voltage changes linearly over time. A digital counter records when the ramp crosses the sampled input; that crossing time represents the input value. In imec’s design, many small slope-ADC elements work in parallel, with their combined output delivering the high aggregate sampling rate.
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The 2026 implementation contains 2,048 channels. Imec identifies two patented techniques intended to address the challenges of using a large array:
- Slope-signal linearization corrects distortion in the ramp-based conversion process.
- Switched input buffers feed the array while minimizing electrical loading on the input.
The approach trades a smaller, slower conversion element for a much larger number of parallel elements. The array supplies throughput without requiring every individual converter to run at the full aggregate sampling rate.
Why optical links need faster electrical converters
Optical transceivers convert between electrical and optical signals. As AI workloads and cloud services increase traffic among servers, storage, and networking equipment, transceivers must handle faster electrical signals while keeping area, power use, and signal integrity under control. High-speed ADCs are one part of that electrical interface.
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For wireline sampling rates above 100GS/s, conventional time-interleaved successive-approximation-register (SAR) ADC designs can require many high-speed channels. More channels mean more interconnect, and those interconnects add parasitic capacitance that can increase energy use and complicate signal delivery. Imec presents its parallel slope-ADC architecture as an alternative intended to reduce some of these scaling pressures.
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How the 2026 result compares with imec’s earlier prototype
Imec’s 2026 result follows a 2024 proof of concept. The figures below are results reported by imec for two different prototypes; they do not establish an independently measured, like-for-like comparison.
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| Reported measure | 2024 proof of concept | 2026 prototype |
|---|---|---|
| Resolution | 7-bit | 7-bit |
| Sampling rate | 42GS/s | 175GS/s |
| Process technology | 16nm FinFET | 5nm FinFET |
| Number of slope-ADC channels | 768 | 2,048 |
| Core area | 0.07mm² active core area | 250 × 250µm² core |
| Power or conversion energy | 96mW power consumption | 2.2pJ per sample conversion energy; total power not stated in the announcement details summarized here |
In 2024, imec said the prototype was at least twice as compact as conventional approaches and that the architecture could scale toward 150GS/s and beyond. The 2026 prototype’s reported 175GS/s sampling rate is above that earlier stated scaling target, but the available figures do not show that every design condition or measurement method was identical across generations.
What the announcement does—and does not—establish about SAR alternatives
Imec argues that its slope-ADC approach can push beyond the performance limits of SAR-based ADC architectures at ultra-high speeds. The rationale in the announcement is that conventional time-interleaved SAR designs need many high-speed channels, with associated interconnect and parasitic-loading costs, while the slope design distributes conversion across compact parallel elements.
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There is no numeric, like-for-like SAR comparison in the reported figures: no named competing ADC, matched test conditions, comparative core area, conversion energy, or measured channel count. The 175GS/s rate, 7-bit resolution, area, and energy therefore describe imec’s prototype; they do not by themselves demonstrate superiority over every SAR implementation or establish suitability for a particular transceiver.
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How the ADC fits imec’s wireline program
The ADC is part of a broader imec wireline effort that includes 5nm and 3nm CMOS ADC, DAC, and PLL work. The program also includes a 100Gbaud PAM-4 clock-and-data-recovery (CDR) circuit described as compatible with imec’s ADC approach. Separately, imec’s optical-transceiver research addresses 100–130Gbaud intensity-modulation direct-detection (IMDD) and coherent transceivers, equalization, clock and data recovery, and heterogeneous integration of electronic and photonic devices.
Those program areas provide context for the intended ecosystem, but do not mean that the 175GS/s ADC is already integrated into a shipping optical transceiver or that it supports every data rate and modulation format listed in the wider research program.
Can you buy the ADC?
No retail component or off-the-shelf ADC product is described in the announcement. Imec presents the chip as a research prototype and technology platform, and invites fabless companies developing wireline connectivity building blocks to join its ADC and DAC research programs. It also says licensing options are available for its underlying IP portfolio.
Licensing terms, pricing, geographic availability, and the specific availability of this implementation are not published in the announcement. Companies considering a program or license would need to confirm those details with imec. The announcement does not provide a basis for treating the prototype as a purchasable standalone chip.
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