On Cortex-M0 and Cortex-M0+, Sleep and Deep Sleep are architectural low-power modes, not fixed current-consumption settings. The SLEEPDEEP bit in the System Control Register selects which mode a wait instruction requests: clear for Sleep, set for Deep Sleep. What Deep Sleep actually powers down—and how much current or wake latency you get—depends on the specific microcontroller and board.
Sleep vs. Deep Sleep: what changes?
Both modes stop the processor from executing while it waits. The distinction is how deeply the surrounding system is asked to reduce power. In the System Control Register, SLEEPDEEP clear selects Sleep; set selects Deep Sleep.
| Mode | Architectural selection | What it means in practice |
|---|---|---|
| Sleep | SLEEPDEEP is clear |
The processor clock normally stops. The surrounding MCU decides which other clocks and peripherals continue running. |
| Deep Sleep | SLEEPDEEP is set |
A request to the surrounding system for deeper shutdown. Depending on the MCU, this may stop the system clock or switch off resources such as the PLL and flash; it does not guarantee those actions on every device. |
Arm’s Cortex-M0 Devices Generic User Guide states that implemented sleep modes are implementation-defined. Consequently, the core name alone does not tell you the current draw, retained state, available wake sources, or time to resume. Those are properties of the MCU implementation and its configuration.
How WFI and WFE enter low-power states
WFI: wait for an interrupt
WFI (Wait For Interrupt) stops instruction execution and enters the selected sleep mode until a qualifying interrupt or debug event occurs. For typical interrupt-driven idle code, CMSIS provides __WFI(). Whether a particular pending or enabled interrupt qualifies depends on the interrupt configuration and architecture rules, so verify the behavior for your MCU and firmware setup.
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WFE: wait for an event
WFE (Wait For Event) uses the processor’s event register. If that register is clear, WFE waits for an event; if it is set, WFE clears it and returns immediately. CMSIS provides __WFE() for event-driven waits. A WFE loop must account for this clear-and-return behavior: an event already recorded can make the instruction return without sleeping.
Review SEVONPEND when choosing WFE. This setting affects whether a pending interrupt can generate an event, including cases where the interrupt is disabled. Do not assume WFE and WFI react identically to the same interrupt state.
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Configure Deep Sleep safely
SLEEPDEEP selects the architectural class; it does not configure the MCU’s regulator, clocks, peripherals, or memory retention for you. Apply the vendor’s required peripheral and power setup before requesting Deep Sleep, and restore any changed system state after wake.
- Read the exact MCU reference manual. Identify the vendor’s low-power mode corresponding to the core’s Deep Sleep request, along with its required regulator, clock, and power-control settings.
- Choose what must remain available. Configure memory retention and the peripheral or interrupt sources that need to wake the device. Confirm which SRAM banks, timers, clocks, flash, and other peripherals survive the selected mode.
- Prepare the system before sleeping. Put peripherals into their required low-power states and configure vendor-specific controls before setting
SLEEPDEEP. - Use the wait instruction suited to the design. Use CMSIS
__WFI()for interrupt-driven idle or__WFE()for event-driven waits, with the event-register behavior andSEVONPENDsetting in mind. - Restore and verify after wake. If the vendor mode changes clocks or other system state, re-establish what the application requires before using affected peripherals or timing services.
Sleep-on-Exit for interrupt-driven firmware
Sleep-on-Exit can return the processor to Sleep or Deep Sleep when an exception handler finishes. It suits firmware that has no foreground work between interrupt handlers: after servicing an event, the core can wait again rather than run an idle loop. Before enabling it, ensure that the application does not need foreground code after the handler returns.
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WIC, wake latency, and timing
An implementation may include an optional Wakeup Interrupt Controller (WIC). In Deep Sleep, a WIC can allow much of the core to be power-gated while still detecting a wake-up interrupt. That deeper shutdown can add restoration time; the implementation may also stop SysTick. Check the MCU documentation if wake latency or timer continuity matters, and validate the behavior in the selected mode.
Why current may remain high in Deep Sleep
Setting SLEEPDEEP only requests the architectural mode. The MCU may still draw substantial current if its implementation or configuration leaves power-hungry resources active, or if the measurement includes board-level loads. Diagnose the actual device and board rather than treating the core label as a current specification.
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- Check the vendor mode mapping and setup. Confirm the intended MCU power mode is selected and all required regulator, clock, and power controls are configured.
- Find what remains powered. Use the reference manual to check clocks, PLL, flash, SRAM banks, timers, peripherals, and retention settings for that exact mode.
- Check wake sources and activity. Peripheral activity or repeated wake-ups can prevent the system from remaining in its deepest state for long.
- Account for the board. Regulators, sensors, interfaces, and other board circuitry can draw current independently of the processor’s low-power state.
- Measure representative firmware. Debugger attachment can perturb current or wake behavior. Compare measurements with and without debug hardware connected when practical, and use the MCU vendor’s prescribed measurement conditions.
Arm’s Cortex-M0 and Cortex-M0+ architecture documentation does not establish one universal Deep Sleep current or wake-latency value. Measure the exact MCU and board in the intended configuration; report the mode, retained resources, board setup, and measurement conditions alongside any result.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What to compare between Cortex-M0/M0+ microcontrollers
The core designation does not guarantee equivalent low-power behavior across MCUs. When choosing or evaluating devices, compare these implementation-level characteristics in their vendor documentation:
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- Attainable current in the specific mode and the conditions under which it is specified.
- Wake latency and clock-restart behavior.
- SRAM and register retention options.
- Whether flash, system clocks, and PLL remain available or must be restored.
- Which peripherals and interrupt sources can wake the device.
- Regulator requirements and whether an optional WIC or vendor-specific retention controller is present.
- Debug behavior and any effect on low-power entry, wake, or measurement.
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