Short answer: Microchip’s RTG4, RT ProASIC3 and RTAX-S families address different space-design needs. RTG4 combines hardened logic with high-speed SerDes; RT ProASIC3 offers nonvolatile Flash operation and low-power features; RTAX-S emphasizes SEU-hardened sequential logic and error-corrected embedded memory. Choosing among them requires comparing the mission’s radiation environment, performance and power needs, package and screening requirements—not just one radiation rating.
These products were developed under the Microsemi name and are now documented and sold under Microchip. The figures below are vendor-published specifications, not a substitute for reviewing the applicable device radiation reports and procurement requirements.
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How do the three FPGA families differ?
| Family | Core strengths | Published radiation information | Published density and interfaces | Package and qualification notes |
|---|---|---|---|---|
| RTG4 | Hardened fabric and high-speed SerDes | Microchip reports TID above 100 krad, and configuration-memory upset and SEL immunity above LET 103 MeV-cm2/mg. | Up to 151,824 registers and 24 SerDes lanes at 3.125 Gbps per lane, per Microchip RTG4 product documentation. | QML Class V ceramic options and a JEDEC-qualified radiation-tolerant plastic BGA option are listed by Microchip. |
| RT ProASIC3 | Nonvolatile Flash operation, instant power-up and Flash*Freeze state retention | Microchip lists 25 krad TID; device-family SEU and SEL figures are given in its product information. | RT3PE600L: up to 600,000 system gates and 270 user I/Os; RT3PE3000L: up to 3,000,000 system gates and 620 user I/Os, per Microchip’s RT ProASIC3 page. | Hermetic CQFP and CCGA/LGA package options and QML qualification categories are listed by Microchip. |
| RTAX-S | SEU-hardened flip-flops and error-correction encoding for embedded SRAM | Microchip describes the hardened logic and corrected memory; consult the applicable device reports for radiation data. | Not stated in the cited Microchip RTAX-S product information. | Package and qualification choice depends on the device and mission requirements. |
The published values are not interchangeable measures of overall radiation performance. For example, RTG4’s TID figure does not describe its SEU rate, and a family-level feature does not establish the suitability of every device, package or screening flow for a particular mission.
What makes RTG4 a candidate for high-speed payloads?
Microchip describes RTG4 as a fourth-generation Flash-based FPGA that integrates high-performance SerDes with its FPGA fabric. Its combination of register capacity and serial interfaces makes it a natural first candidate when a design needs substantial logic alongside high-speed communications or payload data paths.
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- Radiation features: Microchip lists TID above 100 krad, configuration-memory upset immunity above LET 103 MeV-cm2/mg, and SEL immunity above LET 103 MeV-cm2/mg.
- Logic and memory protections: The family includes SEU-hardened registers with built-in TMR, EDAC in SRAM, and hardened global clocks and resets.
- Packages: Listed options include QML Class V ceramic CG(G)A/LG(G)A 1657 and CQ(G)FP 352 packages, as well as a JEDEC-qualified FC(G)1657 RT mil-plastic BGA.
Those features can reduce some system-level mitigation work, but they do not remove the need to evaluate the mission’s radiation environment, device reports and package qualification. Microchip also documents an RTG4 FPGA Development Kit for evaluating data transmission, serial connectivity, bus interfaces and high-speed designs.
When does RT ProASIC3 make sense?
RT ProASIC3 is aimed at designs where nonvolatile operation and power matter. Its Flash-based configuration is live at power-up, without a configuration boot sequence. Microchip’s datasheet describes Flash*Freeze as shutting off clocks and inputs to the FPGA core while retaining data.
In the 2022 Microchip/Microsemi RT ProASIC3 datasheet, Microchip reports a 40% reduction in dynamic power and a 50% reduction in static power. Treat these as vendor-published datasheet figures; actual power depends on the design and operating conditions.
The product page lists RT3PE600L and RT3PE3000L, with up to 600,000 and 3,000,000 system gates respectively. Their published maximum user-I/O counts are 270 and 620. The same page lists embedded RAM, hermetic CQFP and CCGA/LGA packages, and QML qualification categories.
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Outbyte PC Repair FREEClear out junk files and repair common Windows errorsFree Scan →Outbyte Driver Updater FREEScan for outdated or missing drivers - takes under a minuteDriver Scan →For radiation, Microchip lists 25 krad TID. Its product information also reports worst-case GEO SEU below 1E-10 errors per bit-day, SEL immunity above LET 68 MeV-cm2/mg and SEU immunity above LET 96 MeV-cm2/mg. These are vendor-published figures; review the relevant test reports and device-specific conditions before using them in a mission analysis.
What should designers know about RTAX-S?
Microchip describes RTAX-S as providing SEU-hardened flip-flops without user intervention and embedded SRAM with error-correction encoding. That combination makes the family relevant when hardened sequential logic and corrected memory fit the design’s requirements.
Microchip cites flight heritage for RTAX-S on Sentinel-2, KOMPSAT-3, ExoMars, GOES-R, Galileo, BepiColombo, MTG, the James Webb Space Telescope, GPS III and Iridium. This is vendor-stated family heritage; it does not establish that every RTAX-S device, package or screening flow is suitable for a new mission. Select against the actual device reports and procurement requirements.
What do the radiation ratings mean?
Total ionizing dose (TID)
TID accumulates over a mission’s radiation exposure. A TID rating is one part of a radiation assessment, not a summary of all radiation behavior. A device’s stated tolerance must be considered against the expected mission dose and applicable test conditions.
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Single-event upset (SEU)
An SEU is a logic or memory disruption caused by an energetic particle. For an FPGA, distinguish configuration-memory upsets from user-register and embedded-memory upsets. Hardened registers, TMR and EDAC can affect the mitigation required at system level, but the design still needs an assessment of which structures are covered and what residual upset behavior applies.
Single-event latch-up (SEL)
SEL is a high-current state that can interrupt operation and may require power cycling. Microchip’s reliability guidance says devices with an SEL threshold LET below 37.5 MeV-cm2/mg are considered unsuitable for space applications. Check the threshold and test conditions for the exact device under consideration.
Transient response and test conditions
Radiation performance also depends on transient behavior and on how testing was conducted. When comparing device reports, examine particle species and energy, test bias, cross-section, package and lot alongside the mission orbit and duration. A single TID or LET number cannot capture all of those differences.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How should you choose a family for a mission?
- Set the functional requirement: establish required logic density and any DSP or SerDes throughput before narrowing the candidates.
- Model the radiation environment: determine the mission’s TID and single-event environment for its orbit and duration, then compare those requirements with device-specific reports.
- Define mitigation coverage: identify whether configuration memory, registers and embedded SRAM need protection, and assess what the family’s hardened features and correction mechanisms cover.
- Check power and thermal limits: evaluate the design’s operating modes and thermal budget; do not assume a datasheet power-reduction figure predicts the completed design’s consumption.
- Confirm package and qualification: match the exact package, qualification category and required screening flow to the mission and procurement plan.
- Verify supply and development support: check supply continuity and authorized support, along with tool and evaluation-board availability. For hands-on RTG4 evaluation, Microchip documents an RTG4 FPGA Development Kit.
As a starting point, consider RTG4 for high-speed payload processing or communications when its density and SerDes fit; RT ProASIC3 when nonvolatile instant power-up and Flash*Freeze align with low-power design needs; and RTAX-S when its hardened sequential logic and corrected memory match the device-level requirements. These are screening directions, not mission approvals.
How should devices be procured?
For a flight design, procure through an authorized aerospace electronics distributor after confirming the exact part, package, grade, screening, qualification and lead time. A family-level specification or heritage reference is not a substitute for confirming those details on the selected device and lot.
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