Several RISC-V processor IP options target automotive functional-safety designs at ASIL B or higher, including SiFive’s Automotive E6-A and E7-A, Andes’ N25F-SE and D23-SE, and Fraunhofer IPMS’s EMSA5-FS. Their claims are not interchangeable: some describe certification, others safety support or a core intended for safety development. And none makes an entire vehicle system safe by itself. AI can help detect anomalies or assess plausibility, but deterministic mechanisms must retain authority over safety-critical control.
What ASIL B means for a RISC-V core
RISC-V is an open instruction-set architecture, not a processor with a single safety certification. ISO 26262 evidence applies to a particular implementation and its defined scope, and ultimately contributes to a system-level safety case. RISC-V International puts the distinction plainly: “No ISA is certified. The ISA is certifiable; implementations are certified.”
For an automotive design, that means asking what the supplier’s claim covers: a processor IP product, a safety element out of context (SEooC), a development process, or a particular integrated product. Even a certified IP block does not automatically certify the SoC, software, vehicle function, or complete safety case that uses it.
ASIL B is a functional-safety integrity level defined by ISO 26262. It is not a general quality grade or proof that a processor will meet a project’s timing, diagnostic, or fault-tolerance requirements. The integrator must establish that the core’s assumptions, safety mechanisms, software, and surrounding hardware fit the item-level safety concept.
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RISC-V cores with automotive safety claims
The supplier descriptions below differ in scope and specificity. “Not stated” means the cited supplier material summarized here does not establish the detail; it is not evidence that the feature is absent.
| Core | Safety claim and scope | Safety mechanisms or determinism described | AI, DSP, or vector capabilities described | Stated application context |
|---|---|---|---|---|
| SiFive Automotive E6-A / E7-A | SiFive’s automotive product pages list ISO 26262 ASIL B, ASIL D, and split-lock support for these 32-bit processor families. The precise certification artifact and scope for a specific configuration must be confirmed with SiFive. | Split-lock support is listed. Other mechanisms, diagnostic coverage, memory behavior, and interrupt determinism are not stated in the available product description. | Not stated. | ADAS/AD, IVI, body, zonal, powertrain, central compute, and safety-island applications. |
| AndesCore N25F-SE | Andes’ product page states support for ISO 26262 ASIL B functional safety in automotive applications. The specific certification scope is not stated in that description. | Not stated in the cited product description. | Not stated in the cited product description. | Automotive functional-safety applications; more specific deployment roles are not stated. |
| AndesCore D23-SE | Andes announced on 2026-08-18 that D23-SE achieved ISO 26262 ASIL-B and ASIL-D certification with full compliance. The announcement describes it as a Safety Element out of Context (SEooC). | Specific redundancy, lockstep, ECC, memory-protection, and diagnostic-coverage details are not stated in the announcement summary. | Andes describes vector processing, DSP capabilities, its Automated Custom Extension framework, and an end-to-end AI hardware/software stack. | Safety-oriented automotive processor IP; the announcement does not specify a single vehicle domain. |
| Fraunhofer IPMS EMSA5-FS | Fraunhofer IPMS positions this safety-oriented core for ISO 26262 functional-safety development up to ASIL D. That positioning is not the same claim as a named certification of the integrated product. | 32-bit, in-order, five-stage core; integrated dual-mode or triple-mode redundancy, optional lockstep, ECC protection for buses, configurable memory-protection unit, privilege modes, and reset/safety-manager modules. These features do not by themselves establish project-specific diagnostic coverage or worst-case execution time. | Not stated. | Safety-oriented embedded processor applications; a narrower automotive domain is not stated. |
How to read the supplier claims
SiFive names ASIL levels and split-lock support, but a design team should obtain the applicable safety manual, certificate or assessment evidence, configuration limits, and integration assumptions before treating that listing as evidence for a particular project. Andes’ D23-SE announcement is more explicit about a certification outcome and SEooC scope; that still leaves system integration and the integrator’s safety case to complete. Andes’ N25F-SE page states ASIL B support, which should not be silently upgraded to a broader certification claim.
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EMSA5-FS stands out in the supplied technical description for enumerating hardware safety features and a bounded pipeline structure. Those are useful design facts, not a substitute for measured timing analysis, diagnostic evidence, or a project-specific safety assessment. An in-order, five-stage description alone does not prove deterministic end-to-end behavior when caches, memory systems, peripherals, interrupts, and software are included.
Where AI belongs in a safety-critical design
AI can support functions such as anomaly detection, plausibility checks, and predictive maintenance. RISC-V International’s automotive guidance describes AI as able to inform and monitor while a deterministic mechanism retains final authority. In practical terms, an AI workload may flag an unusual sensor pattern or request closer inspection; a separately justified safety mechanism should decide whether to limit torque, enter a safe state, or continue operation.
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An AI accelerator or vector extension does not itself satisfy functional-safety requirements. The safety case still has to address faults in the processor, accelerator, memory, data paths, software, and input data, as well as the consequences of an incorrect or late AI result. If the AI output can directly command a safety-critical actuator, its behavior and failure handling must be covered by the system’s safety concept rather than assumed safe because the core supports AI workloads.
How to compare cores for an ASIL B design
Start with the safety goal and system architecture, not with the processor brand or AI feature list. Compare candidate IP against the evidence and constraints your project actually needs:
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- Claim scope: Ask whether the evidence applies to the exact IP version and configuration, and whether it is a certification, SEooC assessment, safety-process claim, or development positioning. Get the certificate or assessment scope and any restrictions.
- Fault detection and reaction: Identify available redundancy, lockstep, ECC, memory protection, safety management, fault reporting, and recovery behavior. Request diagnostic coverage data and the assumptions behind it; a feature name alone does not quantify protection.
- Timing and determinism: Request information needed to establish worst-case execution time, interrupt latency, memory-system contention, and behavior under faults for the intended configuration. Check whether AI or vector workloads can delay or interfere with a safety task.
- AI architecture: Determine whether vector, DSP, custom-extension, or separate accelerator capabilities are included, optional, or part of a software stack. Establish how the safety partition observes or limits those workloads.
- Integration evidence: Review the safety manual, integration guide, safety analysis artifacts, tool qualification information where applicable, software support, and assumptions about clocks, memory, peripherals, and external monitors.
- Product fit and economics: Match the core to its intended role—such as a safety island, MCU-class controller, zonal controller, or ADAS compute—and obtain project-specific area, power, performance, licensing, and support terms. These figures and terms are configuration- and contract-dependent and are not established in the supplier descriptions summarized above.
What the integrator still has to prove
Processor IP is one element in a larger safety argument. The SoC integrator, Tier-1, or vehicle manufacturer must show how the selected core and its configuration meet the item’s safety requirements, including interactions with software, memory, peripherals, communications, and power or clock supervision.
- Define the safety role. Decide whether the core runs a safety function, monitors another processor, hosts an AI workload, or performs more than one role. Define the safe state and response time for relevant faults.
- Map assumptions to the implementation. Check the supplier’s safety documentation against the actual IP revision, configuration, toolchain, SoC, and operating conditions. Record which assumptions the integration must satisfy.
- Design partitioning and fault response. Specify how safety-related software is isolated, how faults are detected and reported, and what independent mechanism can constrain or override an unsafe output.
- Validate the complete path. Assess timing, diagnostics, fault injection and recovery, and interference across the processor, AI hardware if present, memory, peripherals, and software. Feed the resulting evidence into the system safety case.
The useful choice is therefore not simply “which RISC-V core is ASIL B?” It is which specific core, evidence package, safety mechanisms, and integration model can support the project’s safety goals without giving an AI workload unverified control over the final decision.
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