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You can use an FPGA’s LVDS pairs as SERDES lanes only when the device provides legal LVDS-capable pins and the appropriate I/O SERDES resources. The differential pair supplies the electrical connection; a working lane also needs serialization or deserialization, a clocking and sampling plan, word alignment, timing constraints, and hardware verification. “Every pair” therefore means every pair that is legal for the chosen device, bank, and placement—not every pair on the package automatically.
What does it take to make an LVDS pair a SERDES lane?
LVDS describes a differential electrical signaling standard, not a complete serial data link. A pair can carry a serial stream, but the FPGA must also convert between that stream and the parallel data used by its logic. The receiver must sample at the right time and determine where each parallel word begins.
Plan the lane as a chain of related resources and functions:
- Electrical I/O: legal differential pins, a compatible I/O bank and voltage standard, and any required on-chip termination.
- SERDES: a supported transmitter serializer, receiver deserializer, or both, configured for the required width and operating mode.
- Clocking and sampling: a forwarded clock for a source-synchronous link, or an explicitly supported clock-recovery method for an asynchronous link.
- Alignment: logic to find the boundary between serial bits and parallel words, and—if there are multiple lanes—to deskew and align the lanes.
- Implementation and verification: timing constraints, legal placement, reset behavior, and tests for data integrity and reacquisition after errors.
Some FPGA families let a differential pair be configured as either a transmitter or a receiver, but that does not make every package pair interchangeable. Intel’s Stratix 10 documentation describes true LVDS on its LVDS I/O banks, differential reference-clock support for the I/O PLL, and transmitter or receiver configuration for each LVDS pair. Its LVDS SERDES IP can place transmit and receive channels in one bank in duplex mode. These are device-family capabilities, not a promise that any two pins can form any lane.
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What should you decide before assigning pins?
Define the link contract
Write down the interface requirements before choosing pins or generating IP. Specify the payload width and word rate, serial bit rate, encoding, framing or training pattern, lane polarity, whether clocking is source-synchronous or asynchronous, and acceptable latency. Also decide how the receiver should recognize valid data after startup or a loss of alignment.
The serialization factor connects the parallel interface to the serial stream. For example, an N-bit word serialized over N bit intervals produces N serial bits per word; the required rate and clock relationships depend on the selected SERDES mode and device IP. Use the vendor’s family-specific documentation and generated-IP configuration for the actual clock rates and interface behavior rather than assuming a generic relationship applies identically across families.
Check resources and placement together
Before fixing PCB pin assignments, check the device pinout and family documentation for true differential pairs, LVDS-capable banks, clock-capable pins, SERDES channel locations, reference-clock routes, and termination options. Confirm that the intended combination of transmitters and receivers, factors, and clocks can be placed legally. Intel’s LVDS IP includes placement and legality checks; run those checks with the proposed assignments rather than treating a package pin list as proof of a valid SERDES arrangement.
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Choose a family-specific implementation
Use the FPGA vendor’s dedicated I/O SERDES or LVDS/GPIO IP where available. A fabric shift register is not a substitute for dedicated high-speed I/O resources when the intended rate depends on those resources’ clocking and timing behavior. Configure transmit and receive paths independently as needed: a design may use a serializer, a deserializer, or both.
For AMD/Xilinx 7-series devices, OSERDESE2 is a dedicated parallel-to-serial converter with SDR and DDR operation. AMD documents native serialization up to 8:1, extendable to 10:1 or 14:1 through width expansion. ISERDESE3 is a dedicated serial-to-parallel block for high-speed source-synchronous interfaces. Use the relevant family’s clocking and IDELAY resources where required, and add framing and bitslip control in fabric.
How do you configure clocking and sampling?
For a source-synchronous link
In a source-synchronous interface, the transmitter sends a clock along with the data. Route and constrain that forwarded LVDS clock, and account for data-to-clock skew at the receiver. The receiver needs a sampling phase that captures data reliably across the expected skew and signal margin.
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Intel’s Arria 10 LVDS documentation distinguishes non-DPA, DPA, soft-CDR, and bypass receiver modes. In non-DPA mode, the designer manages data-to-clock skew. DPA automatically selects a sampling phase. Soft-CDR is intended for asynchronous clocking and produces a recovered clock. Choose among these only where the selected device and IP support the required mode; the labels do not imply identical behavior across FPGA families.
For an asynchronous link
Do not assume that an ordinary LVDS input can recover an independent transmitter’s clock. Use a supported clock-recovery function, such as a family’s soft-CDR mode, only if its documented behavior fits the link. Account for the recovered-clock domain in downstream logic and establish the required clock-domain crossing behavior. If the device/IP does not support the intended asynchronous link, use a different architecture rather than treating DPA, a forwarded-clock receiver, and CDR as interchangeable.
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Configure the serialization factor, SDR or DDR mode, parallel data width, interface clock, fast serial clock, and reset behavior in the vendor IP. The legal combinations and clocking details vary by family. Confirm how the IP handles reset, when its outputs are valid, and how alignment control interacts with reset before connecting the parallel interface to system logic.
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How do you align words and multiple lanes?
Find the word boundary
A deserializer can produce parallel words without knowing which serial bit is the first bit of a transmitted word. Send a known training sequence or comma/synchronization marker, then use bitslip or the IP’s supported alignment control to move the apparent boundary until the receiver recognizes the expected pattern. Verify lane polarity as part of bring-up; a reversed differential pair may require an allowed polarity correction or a board-level change, depending on the device and interface.
Deskew and align a lane group
For multiple serial lanes, finding each lane’s word boundary is not enough. Use a common alignment marker and per-lane deskew so words from different lanes represent the same point in the transmitted stream before presenting them as one parallel bus. Define how the receiver detects loss of alignment and returns to a known state.
What must you constrain and verify?
Constrain the actual interface
Apply the differential I/O standard and termination required by the selected device and board. Constrain input and output delays against the relevant clock, define generated clocks where appropriate, and account for the fast I/O clocks and interface clocks used by the SERDES. Use false-path or clock-domain-crossing constraints only where justified, and apply timing exceptions according to the family’s vendor guidance. A timing report is meaningful only if the constraints describe the real data and clock relationships.
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Verify the link beyond successful elaboration
Check placement and timing, then test the physical link at the intended operating conditions. Confirm eye margin and bit-error behavior, reset recovery, word and lane alignment, and loss-of-lock or loss-of-alignment recovery where applicable. A design that passes synthesis has not by that fact demonstrated reliable sampling or alignment on the board.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Should you use FPGA-native SERDES or an external LVDS chip?
For a new multi-lane design with supported FPGA resources, native SERDES is generally the first option to evaluate: it avoids another conversion component and can keep the datapath close to FPGA logic. An external device can make sense when the interface has a fixed ratio, the FPGA lacks sufficient native resources, or a discrete bridge helps adapt a legacy parallel interface. Compare the actual family limits and board requirements rather than assuming either approach is universally faster or simpler.
| Decision axis | FPGA-native LVDS SERDES | External LVDS SERDES IC |
|---|---|---|
| Pin count and latency | Conversion stays inside the FPGA and usually avoids an additional package or board hop. | Adds a component and board interconnect, but can simplify FPGA logic or retrofit a parallel interface. |
| Clocking | May provide DPA, soft-CDR, dedicated I/O clocks, or family-specific bitslip; availability depends on the family. (Intel Arria 10 and Agilex 3 documentation.) | Depends on the external chip’s clocking and framing scheme; verify compatibility with the FPGA clock domain. |
| Rate and ratio | Device-specific. Examples: Arria 10 factors 3–10; AMD OSERDESE2 up to 8:1 natively, with width expansion to 10:1 or 14:1; Agilex 3 up to 1.25 Gbps with factors 4 and 8. (Intel Arria 10 and Agilex 3 documentation; AMD OSERDESE2 documentation.) | TI’s SN65LV1023A/SN65LV1224B chipset is a documented 10:1 LVDS serializer/deserializer for equivalent parallel-word rates of 10–66 MHz. (TI product documentation.) |
| Bring-up | Requires vendor IP configuration, legal pin placement, timing closure, and alignment logic. | Requires power, termination, package, signal-integrity, and external-chip configuration checks. |
| Typical fit | New designs using a supported FPGA family, especially where low latency or multiple lanes matter. | Fixed-ratio or retrofit interfaces, or designs without adequate native SERDES resources. |
Why can’t one set of settings apply to every FPGA LVDS pair?
Families differ in their I/O architecture, supported SERDES factors, clocking resources, and rate limits. Intel’s 2025 Arria 10 documentation lists serialization factors from 3 through 10 and several receiver modes. AMD’s 2026 OSERDESE2 documentation describes up to 8:1 native serialization with width expansion to 10:1 or 14:1. Intel/Altera’s 2025 Agilex 3 guide specifies true differential HSIO resources, configurable transmitter or receiver direction, on-chip 100-ohm termination, factors 4 and 8, and rates up to 1.25 Gbps, with CDR on specific differential channels. These are published family limits, not general specifications for all LVDS pairs or all FPGA families.
Consequently, pin-level settings and guaranteed rates require the exact FPGA family and a defined link budget. Confirm those against the selected device’s pinout, IP guide, and timing documentation before finalizing the hardware.
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