In 2014, University of California, Santa Barbara (UCSB) researchers reported a high-performance III-V MOSFET with an on-current of 0.50 mA per micrometre of gate width at a specified off-current of 100 nA/µm and a 0.5 V supply. It was a laboratory device built around an ultrathin indium arsenide (InAs) channel—not a commercially available transistor. The result was a condition-specific DC performance record among III-V MOSFETs at the time, not proof that the device had the fastest measured switching speed.
What did the UCSB transistor achieve?
The 2014 UCSB result was reported in the paper “Record Ion (0.50 mA/µm at VDD = 0.5 V and Ioff = 100 nA/µm) 25 nm-Gate-Length ZrO2/InAs/InAlAs MOSFETs,” presented at the Symposium on VLSI Technology. Its headline figure was the current the transistor could deliver while meeting a particular off-current target:
- On-current (Ion): 0.50 mA/µm.
- Off-current (Ioff): 100 nA/µm.
- Supply voltage (VDD): 0.5 V.
- Gate length: 25 nm.
These are reported measurements for that device and test condition. They do not establish a universal ranking against every MOSFET: current figures are meaningful only alongside the gate geometry, voltage, off-current criterion, and measurement method used. In particular, the result is not a direct comparison with an unspecified silicon transistor.
Why “highest-performance” does not mean fastest switching
The phrase “world’s highest-performance” refers to the paper’s historical, condition-specific DC performance claim. On-current describes current drive under stated bias conditions; it is not a measurement of how quickly a transistor switches between logic states. The contemporary EE Times report said the researchers had not measured switching speed and described possible radio-frequency advantages as estimates. Those projections should not be treated as measured speed results.
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The paper also reported other DC characteristics, each at its own stated condition:
| Reported characteristic | Value and condition |
|---|---|
| Subthreshold swing | 77 mV/decade at VDS = 0.5 V for the 25 nm-gate device |
| Minimum subthreshold swing | 61 mV/decade for a 1 µm-gate device at VDS = 0.1 V |
| Peak transconductance | 2.38 mS/µm at VDS = 0.5 V |
Subthreshold swing describes how much gate-voltage change is needed to change current by a factor of ten in the subthreshold region; lower values indicate sharper turn-off under the measurement conditions. The 61 mV/decade figure belongs to a separate, longer-gate device and a different drain voltage, so it should not be presented as another measurement of the 25 nm device at 0.5 V.
What made it a III-V MOSFET?
“III-V” refers to compound semiconductors made from elements in groups III and V of the periodic table. UCSB’s device used InAs as its very thin channel, with indium aluminum arsenide (InAlAs) barriers. InAs is attractive for high electron transport capability; the channel and surrounding structure were engineered to control the gate’s influence and reduce leakage.
The reported device structure included a 2.5 nm InAs channel, InAlAs barriers, and selectively regrown In0.53Ga0.47As source/drain material. Vertical source/drain spacers helped limit leakage without greatly widening the source/drain pitch. The gate stack combined a thin Al2OxNy interfacial layer with a ZrO2 high-k dielectric. The epitaxial structure was grown on semi-insulating InP; the device used a Ni/Au gate and Ti/Pd/Au source/drain contacts.
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The ultrathin channel and gate dielectric support close electrostatic control of the channel, while the dielectric stack provides strong gate-channel capacitance. The vertical spacer spreads the electric field and helps avoid band-to-band tunneling. Together, these choices helped the team pursue high current while keeping off-current to the stated target. They are design features of this experimental device, not evidence that any InAs transistor will achieve the same figures.
Was this transistor made on silicon?
No. The reported record device was grown on an InP substrate. In its 2014 account, EE Times quoted UCSB professor Mark Rodwell discussing the possibility of integration: “The present substrate is InP. Other research groups, including IMEC, have shown that InP can be grown on Si.” That comment concerns a possible integration route; it does not mean this particular record transistor was fabricated on silicon or establish a commercial silicon-compatible product.
Substrate and integration route matter when comparing research devices with silicon technology. A result on InP cannot be assumed to transfer unchanged to silicon, silicon-on-insulator, or a manufacturing process designed for silicon wafers.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Can you buy the UCSB record MOSFET?
No catalog or retail version of this exact transistor is identified in the 2014 report or paper. It was a custom university research device made using a specialized semiconductor process, not a packaged component offered for purchase. Searches for broad terms such as “III-V MOSFET” or “InAs transistor” may find other research or products, but those terms do not identify an equivalent to the UCSB device or guarantee its structure and performance.
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How to interpret the record today
The accurate takeaway is narrow but significant: in 2014, UCSB reported a 25 nm-gate-length InAs-based III-V MOSFET with 0.50 mA/µm on-current at 100 nA/µm off-current and VDD = 0.5 V, alongside strong reported DC characteristics. “Highest-performance” describes that historical claim and its specified comparison context. It should not be read as a current ranking of all MOSFETs, a claim about measured switching speed, or an assertion that the transistor was a silicon device or a purchasable part.
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