The latest approved standard in the Verilog language lineage is IEEE 1800-2023, the SystemVerilog standard. The last standalone Verilog edition was IEEE 1364-2005; the current IEEE 1800 family unifies that Verilog lineage with SystemVerilog, so current references generally use “SystemVerilog” and “IEEE 1800.”
What is the latest Verilog standard?
IEEE 1800-2023 is the latest approved active standard in the Verilog/SystemVerilog lineage. IEEE lists it as superseding IEEE 1800-2017. It defines the syntax and semantics of the SystemVerilog language, including hardware description and verification features.
The IEEE Standards Board approved the standard on December 6, 2023. IEEE published it on February 28, 2024, and ANSI approval followed on February 27, 2025. These are distinct milestones; the standard’s edition year remains 2023.
Why is the latest standard called SystemVerilog?
“Verilog” can refer either to the language lineage broadly or to the older standalone Verilog HDL standard. IEEE says the 1800 family began by merging IEEE 1364-2005 Verilog with IEEE 1800-2005 SystemVerilog. The current unified standard is therefore titled IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language.
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For current standards references, use “SystemVerilog” or “IEEE 1800.” “Verilog-2005” refers specifically to the older standalone edition, not the current unified standard.
IEEE 1800-2023 and IEEE 1364-2005 compared
| Edition | Status | Scope | Dates |
|---|---|---|---|
| IEEE 1800-2023 | Active; supersedes IEEE 1800-2017, according to IEEE SA. | Unified SystemVerilog language standard, covering hardware descriptions and verification features. | Standards Board approval: Dec. 6, 2023; publication: Feb. 28, 2024; ANSI approval: Feb. 27, 2025. IEEE SA. |
| IEEE 1364-2005 | Superseded standalone Verilog standard, according to IEEE SA. | Standalone Verilog HDL specification, including syntax and semantics, SDF constructs, simulation system tasks and functions, compiler directives, PLI, and VPI, as described in the IEEE Xplore record. | 2005 edition; publication and approval dates are not stated in the cited IEEE records. |
What does IEEE 1800-2023 cover?
The standard is broader than RTL syntax alone. IEEE’s IEEE Xplore record describes a language for behavioral, register-transfer-level (RTL), and gate-level hardware descriptions, alongside verification capabilities.
- Testbenches, coverage, and assertions.
- Object-oriented and constrained-random verification constructs.
- APIs for connecting SystemVerilog to foreign programming languages.
Should you use SystemVerilog IEEE 1800-2023?
When you need to identify the current IEEE language standard, cite IEEE 1800-2023. If a book, course, or tool reference says only “Verilog-2005,” it is referring to the historical standalone IEEE 1364 edition. That distinction matters when checking whether documentation addresses the unified language and its verification features.
The IEEE standard specifies the language; it does not by itself establish which features a particular simulator, synthesis tool, or project flow supports. Check the documentation for the specific tool and version you use when feature compatibility matters.
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