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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteUMC and Faraday’s 90-nm work was a dated semiconductor engineering collaboration, not a consumer product launch. Faraday documented a standard-performance core-cell library for UMC’s 90-nm process in August 2002; UMC then reported in January 2003 that Faraday had taped out test chips and completed an initial set of silicon-proven IP and library modules.
What UMC and Faraday prepared
The collaboration targeted process-specific intellectual property (IP) and design services for UMC’s 90-nm process. Faraday’s August 2002 version 0.1 datasheet describes “90nm Standard Performance Generic Core Cells,” tailored to UMC’s 90-nm standard-performance process and intended for high-speed, high-density applications. This was a foundry-specific design library, not a standalone retail product.
The timeline matters because the announcements describe different milestones:
- April 25, 2002: UMC and Faraday announced a cooperative program to develop a broad set of IP elements for UMC’s 90-nm process. The same announcement introduced free low-power and “Fusion” libraries for UMC’s 130-nm process; that offer was separate from the 90-nm development program. UMC’s April 2002 announcement.
- August 2002: Faraday issued its version 0.1 datasheet for the 90-nm standard-performance core cells. Faraday’s 90-nm core-cell datasheet.
- January 30, 2003: UMC said Faraday had taped out several test chips manufactured on UMC’s 90-nm process using Magma design solutions, and had completed an initial comprehensive set of process-optimized IP and library modules. UMC described them as silicon-proven and design-rule compliant. UMC’s January 2003 announcement.
“Silicon-proven” here refers to the company’s report that test chips had been taped out and manufactured; it should not be read as an independent assessment of performance, yield, or customer adoption. H.P. Lin, then Faraday president, attributed the readiness to collaboration with UMC and EDA partner Magma. UMC executive Dr. Fu Tai Liou described the availability of the IP as a step toward wider access to its high-performance process. These were executives’ statements accompanying the announcement, not third-party evaluations.
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What the 2002 standard-cell library included
Faraday’s datasheet counted 416 cells and 120 functions in the documented library. That figure describes the contents of this particular 2002 library document; it is not a performance benchmark or a count for every IP module later associated with the program.
The listed cell families covered combinatorial logic, adders, latches, flip-flops and scan variants, clock-gating, filler, tie, antenna, and delay cells. The library package also documented a range of design-flow views and files:
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- Timing and synthesis models
- A power-analysis model
- DRC/LVS command files and ATPG support
- Documentation
Together, these deliverables indicate that the library was intended to support implementation and verification across multiple stages of an ASIC design flow, rather than provide only a list of logic cells.
Which EDA tools did Faraday document?
The August 2002 datasheet lists historical tool versions, including Synopsys Library Compiler 2000.05, Cadence Verilog-XL 2.7, and Mentor ModelTek 5.4e. Treat these as compatibility information for the dated library documentation only. The cited material does not establish compatibility with current releases of those tools or with present-day design flows.
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A later UMC and Cadence announcement, dated September 7, 2004, described a digital reference flow using Faraday libraries and memories. Although the release said the flow targeted 130 nm and below, its stated silicon validation was on UMC’s 130-nm high-speed process; it is not evidence of 90-nm validation. UMC and Cadence’s 2004 reference-flow announcement.
Was the 90-nm library free?
The available announcements distinguish three things rather than establishing one blanket price. UMC’s April 2002 release explicitly called its 130-nm low-power and Fusion libraries free, while describing the 90-nm work as a cooperative IP-development program. Faraday’s undated free-library service page says the program covers libraries validated for UMC 90 nm and 0.13 micron; it describes basic service as free and advanced support as non-free or available by contacting sales. Faraday’s UMC free-library service page.
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Those descriptions do not establish that every historical 90-nm core or IP deliverable was freely downloadable, or that the same license and support terms apply to the specific August 2002 revision.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Can you get or use the historical library today?
Faraday’s IP-search interface includes a 90-nm technology selector, and its service page continues to refer to UMC 90-nm libraries. Those references do not verify that the specific 2002 library revision is currently available, supported, licensed on the same terms, or compatible with modern tools. The cited sources therefore leave current availability and licensing unresolved; confirm both with Faraday before planning a design around the historical library. Faraday’s IP search interface.
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For context, UMC’s August 2003 announcement expanded Faraday silicon-verified IP offerings across 0.18-, 0.15-, and 0.13-micron processes and described access through UMC’s Gold IP program and IP Master online service. It provides partnership and distribution context, but does not announce a new 90-nm catalog. UMC’s August 2003 IP announcement.
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