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Tezzaron’s PSiRAM was a pseudo-static memory technology announced in 2003 as an alternative to SRAM and DRAM. A company-reported 32-Mbit prototype, made in 90-nm CMOS, was specified at 1.3-nanosecond latency, a 1-nanosecond cycle time and 400-MHz performance in a 2-Mbit × 16 quad-data-rate configuration. It still required refresh, but Tezzaron proposed one version with refresh hidden from the user and another that required user-managed refresh.
What was Tezzaron PSiRAM?
PSiRAM was Tezzaron Semiconductor’s 2003 proposal for a memory design between conventional static RAM (SRAM) and dynamic RAM (DRAM). The name described a pseudo-static approach: the memory needed refresh, as DRAM does, but one planned version was intended to behave externally like standard SRAM by hiding that refresh.
Tezzaron, based in Naperville, Illinois, had been known as Tachyon Semiconductor until mid-2003. The company presented PSiRAM for both discrete memory ICs and embedded memory in systems-on-chip (SoCs). It also planned to license the technology for SoC use.
How did PSiRAM differ from SRAM and DRAM?
The proposed distinction was not that PSiRAM eliminated refresh. It was that its cell and read behavior could combine a refresh-requiring memory design with an SRAM-like interface option. Tezzaron described two planned versions: one with hidden refresh and one requiring user refresh, similar to DRAM.
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| Comparison point | PSiRAM, as described in 2003 | Conventional SRAM | Conventional DRAM |
|---|---|---|---|
| Refresh | Refresh required. Tezzaron planned a hidden-refresh version and a user-refresh version. | Refresh behavior not specified in the 2003 PSiRAM announcement; conventional SRAM does not require periodic refresh. | Refresh required; the user-refresh PSiRAM version was described as working much like DRAM in this respect. |
| Read method | Patented three-transistor cell sensed changes in current, according to Tezzaron. | Not detailed in the 2003 announcement. | Not detailed in the 2003 announcement. |
| Latency and cycle time | Tezzaron reported 1.3-ns latency and 1-ns cycle time for its prototype. | Comparable measurements not stated in the 2003 announcement. | Comparable measurements not stated in the 2003 announcement. |
| Cell density, die area, power and reliability | Comparative values or test results not stated in the 2003 announcement. | Comparative values not stated in the 2003 announcement. | Comparative values not stated in the 2003 announcement. |
| Intended use | Discrete memory ICs and embedded SoC memory; licensing was planned. | Presented as a technology PSiRAM aimed to challenge, not as a directly measured comparator. | Presented as a technology PSiRAM aimed to challenge, not as a directly measured comparator. |
The announcement does not provide enough comparable measurements to establish that PSiRAM was denser, lower-power, more reliable or more broadly interface-compatible than either standard memory type. Those claims should not be inferred from its proposed cell design or prototype speed figures.
How did the three-transistor cell work?
Tezzaron said its patented three-transistor cell detected changes in electrical current rather than measuring voltage. The company presented current sensing as a way to reduce read delay. It also said this design could avoid read-modify-write turnaround for some operations, potentially helping workloads that combine reads and writes.
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These were company claims about the technology; the available announcement does not specify which operations avoided turnaround or provide independent comparative test results.
What did the prototype’s speed figures mean?
Tezzaron reported a 32-Mbit PSiRAM prototype fabricated in 90-nm CMOS. In a 2-Mbit × 16 quad-data-rate configuration, it claimed 1.3-ns latency, a 1-ns cycle time and 400-MHz performance. These are reported prototype specifications, not an independent benchmark or proof that a commercially available part sustained those results in every configuration.
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Latency, cycle time and operating frequency describe different aspects of memory behavior. The announcement supplies all three figures but does not give enough test conditions or a direct SRAM or DRAM comparison to turn them into a general claim that PSiRAM was faster for every workload.
What refresh options were planned?
Tezzaron CTO Bob Patti explained that reads were nondestructive: a read did not necessarily require or trigger refresh. That did not make the memory refresh-free. Patti said the company planned two versions:
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- Hidden-refresh version: refresh would be managed internally so the part would appear to the user as standard SRAM.
- User-refresh version: the user would handle refresh much as with DRAM. Patti said this version would run faster than the SRAM-like version.
The announcement describes planned variants, not evidence that both versions reached production or became available for purchase.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Was PSiRAM a commercial memory product or an SoC technology?
It was announced with both possibilities in view. Tezzaron described PSiRAM as an alternative for discrete memory ICs and systems-on-chip, and said it intended to license the technology for embedded-memory use. The 2003 announcement establishes those plans and a prototype claim; it does not establish current production, retail availability, pricing or present-day licensing terms.
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How does PSiRAM relate to Tezzaron’s later memory work?
PSiRAM belongs to a broader history of Tezzaron memory development, but the later names describe distinct technologies and should not be treated as synonyms for PSiRAM.
- 3T-iRAM: Tezzaron later promoted this as a 72-Mbit synchronous-burst NBT SRAM replacement. A 2004 company release said it supported pipeline and flow-through burst modes up to 250 MHz and announced foundry production with Chartered Semiconductor.
- DiRAM and wafer-stacked memory: Tezzaron’s later technology overview described a “dis-integrated” architecture branded DiRAM, separating bit-cell, controller and I/O functions across wafers that were stacked. A separate 2004 announcement described a wafer-stacked 3D RAM chip tested above 500 MHz with less than two-nanosecond latency.
These later developments provide context for the company’s interest in memory architecture and stacking; they do not verify PSiRAM’s commercial availability or establish that its prototype figures apply to the later products.
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