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Copper is not being replaced by graphene in commercial CMOS on the evidence available here. IBM’s 2017 case for keeping copper was practical: a promising material must be made uniformly, patterned at tiny dimensions, integrated with the rest of the chip process and qualified for reliability—not merely conduct well in theory. IBM’s 2024–2025 work shows that copper remains an established option, while also developing ruthenium and investigating other materials for dimensions where copper becomes harder to use.
Why copper became the interconnect standard
Interconnects are the conductive wires that connect transistors and other circuit elements. They are made in the chip’s back end of line (BEOL), after the transistor structures are formed. A wire material has to do more than carry current: manufacturers must deposit and pattern it consistently, prevent it from damaging nearby structures, and achieve acceptable yield and reliability across a complex process.
IBM says it announced full-scale copper manufacturing in 1997 and shipped copper PowerPC processors in 1998. The transition required solving manufacturing and integration problems, including copper deposition, diffusion barriers and layout. Copper can diffuse into surrounding materials, so it cannot simply be substituted for aluminum without process changes.
In its 2025 history account, IBM says copper wires have about 40% less electrical resistance than aluminum and that the change was forecast to deliver a 15% microprocessor-speed increase. The speed figure is a projection reported in that historical account, not a universal gain for every chip or a current benchmark.
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Why the 2017 argument favored copper over graphene
The November 16, 2017 ExtremeTech article at the center of this title argued that copper could remain useful until CMOS itself was replaced. The concern it highlighted was not that graphene lacked attractive electrical properties; it was that graphene was difficult to manufacture uniformly and consistently at the scale required for chip wiring.
That distinction matters. A material’s conductivity in isolation does not establish that it can be made into reliable, densely packed wires inside a commercial CMOS process. A candidate also has to meet the target dimensions, work with barriers and surrounding layers, withstand operating conditions, and be produced with consistent results. In the UC Davis ECE handout reproducing the article, IBM Fellow Dan Edelstein described copper, sometimes with a thin cobalt cap or other underlayers, as the better practical current-carrying option at the sizes then under discussion.
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Why shrinking wires make copper harder to extend
Copper’s maturity does not make its scaling problem disappear. As wires become narrower, their effective resistivity rises and resistance becomes more troublesome. The barrier or liner needed to isolate copper also takes up a larger share of a very small wire, leaving less room for the conductor. Surface-scattering effects and reliability risks add to the challenge.
IBM Research’s 2024 example for a 2 nm-node copper technology has a 24 nm metal pitch and 12 nm line width. Pitch is the repeated spacing from one line to the next; line width is the width of an individual line. The figures describe that technology example, not a claim that all 2 nm-node wiring has the same dimensions or that copper scales indefinitely.
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At these dimensions, engineers must balance electrical resistance against electromigration—the movement of metal atoms under current—and time-dependent dielectric reliability, which concerns the insulation between neighboring wires over time. A material that improves one metric may still be unattractive if it needs difficult integration steps, harms yield, or fails reliability requirements.
How copper, graphene, ruthenium and semimetals compare
The available IBM work describes a continuing engineering search rather than a confirmed successor. The measurements and readiness statements below are specific to the cited examples; they are not a like-for-like production qualification across all four materials.
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| Candidate | Electrical evidence at small dimensions | Manufacturing and integration | Reliability, barriers and readiness |
|---|---|---|---|
| Copper | IBM reports a 24 nm metal pitch and 12 nm line width in a 2 nm-node technology example (IBM Research, 2024). No resistivity value for that example is stated. | Established CMOS BEOL material with a mature process ecosystem; its adoption required solutions for deposition, diffusion barriers and layout (IBM, 2025 history; IBM Research, 2024). | Rising effective resistivity and reliability challenges complicate further scaling. No universal pitch limit is established by these sources (IBM Research, 2024; 2025). |
| Graphene | No target-pitch line-resistivity measurement is stated in the cited 2017 account (ExtremeTech, Nov. 16, 2017, reproduced in a UC Davis ECE handout). | The 2017 concern was achieving manufacturing uniformity and consistency at the needed scale; the sources do not establish a qualified commercial CMOS BEOL process for graphene. | The cited sources do not establish that graphene is permanently ruled out or provide comparative electromigration, dielectric-reliability, thermal-budget, cost or yield results. |
| Ruthenium | IBM Research reported demonstrated subtractive ruthenium lines at 16 nm pitch with measured resistivity below 20 micro-ohm-centimeters (2025). | The result demonstrates a candidate at an ultra-scaled pitch; it does not establish mass-production readiness or compatibility with every existing BEOL flow. | The cited result does not establish commercial qualification, yield, cost, or a complete reliability comparison with copper. |
| Topological semimetals | The cited 2025 IBM work says the materials were not yet sufficiently conductive to compete with copper; a specific line resistivity or target pitch is not stated. | Exploratory candidate class; manufacturing uniformity and integration readiness are not established in the cited work. | No commercial CMOS replacement or production qualification is established by the cited 2025 work. |
What may come after copper
There is no established single successor in the cited work. IBM’s approach is to extend copper where it remains practical while investigating alternatives for pitches at which copper’s resistance becomes unacceptable. Ruthenium has a measured result at 16 nm pitch, but a demonstrated line is not the same as a material ready for high-volume chip production. Topological semimetals remain exploratory in the 2025 work, and the reported conductivity was not yet competitive with copper.
Any eventual transition would depend on more than a favorable resistivity result. A candidate must perform at the intended line dimensions, be manufacturable with sufficient uniformity, fit the BEOL process and its thermal budget, meet electromigration and dielectric-reliability requirements, and offer acceptable yield and cost. The cited sources do not settle those questions for graphene, ruthenium or topological semimetals as a complete commercial replacement.
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How to read IBM’s “copper holds the line” position
The 2017 claim is best understood as a manufacturing judgment about the alternatives available then, not a prediction that copper will remain the wiring material forever. IBM’s later work supports the narrower point that copper’s process maturity gives it staying power, even as shrinking dimensions make it electrically and technologically more difficult. Its 2024 and 2025 research also makes clear that IBM is testing ways beyond copper rather than treating the material as a permanent answer.
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